IP Library › Granted Patent US 11,735,467
Granted Patent B2
US 11,735,467 · App. 17/558,848 · Granted Aug 22, 2023

Airgap formation processes

Inventors: Ashish Pal (Hayward, CA); Gaurav Thareja (Santa Clara, CA); Sankuei Lin (Los Gatos, CA); Ching-Mei Hsu (Mountain View, CA); Nitin K. Ingle (San Jose, CA); Ajay Bhatnagar (Saratoga, CA); Anchuan Wang (San Jose, CA)
Assignee: Applied Materials, Inc.
H01L21/764H01L21/823814H01L21/823821H01L21/823864H01L21/823878H01L27/0924H01L29/0649H01L29/6656H01L29/66795H01L29/785H01L29/7851H01L29/41791
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Quick Facts
Patent No.
US 11,735,467
App. No.
17/558,848
Granted
Aug 22, 2023
Kind
B2
Abstract

Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

Claims (10)

1. A semiconductor structure comprising:

a substrate;

a gate structure overlying the substrate and formed in a first direction across the substrate;

a fin overlying the substrate and formed in a second direction across the substrate, wherein the second direction is normal to the first direction, and wherein the fin intersects the gate structure;

a spacer structure adjacent the gate structure, wherein the spacer structure comprises:

a first layer adjacent the gate structure and extending a first distance laterally outward from the gate structure over the fin and the substrate; and

a second layer laterally outward from the first layer and contacting the first layer at the first distance, wherein an airgap is at least partially defined between a portion of the first layer adjacent the gate, a portion of the first layer overlying the substrate, and the second layer; and

a source/drain material formed about the fin external to the spacer structure, wherein at least one intervening layer of the spacer structure is included between the source/drain material and the airgap.

2. The semiconductor structure of claim 1 , wherein the first layer and second layer comprise one or more materials selected from the group consisting of silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, silicon oxide, a metal oxide, and a metal nitride.

3. The semiconductor structure of claim 1 , further comprising a contact etch stop layer positioned laterally outward of the spacer structure in a direction from the gate structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2021
From: PAL, ASHISH; THAREJA, GAURAV; LIN, SANKUEI; HSU, CHING-MEI; INGLE, NITIN K.; BHATNAGAR, AJAY; WANG, ANCHUAN
To: APPLIED MATERIALS, INC.
Reel/Frame 058563/0717 →
Continuity (3)
Division 16277104 · Feb 15, 2019
Provisional Application 62631179 · Feb 15, 2018
Related Publication 20220115263A1 · Apr 14, 2022