IP Library › Granted Patent US 11,955,509
Granted Patent B2
US 11,955,509 · App. 17/559,176 · Granted Apr 9, 2024

Metal-insulator-metal capacitor

Inventors: Jihyung Kim (Seoul, KR); Jeonghoon Ahn (Seongnam-si, KR); Jaehee Oh (Seongnam-si, KR); Shaofeng Ding (Suwon-si, KR); Wonji Park (Suwon-si, KR); Jegwan Hwang (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L28/65H01L23/5223H01L28/87
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Quick Facts
Patent No.
US 11,955,509
App. No.
17/559,176
Granted
Apr 9, 2024
Kind
B2
Abstract

A metal-insulator-metal capacitor includes a first electrode disposed in a first region of an upper surface of a substrate, a second electrode covering the first electrode and extending to a second region surrounding an outer periphery of the first region, a third electrode covering the second electrode and extending to a third region surrounding an outer periphery of the second region, a first dielectric layer disposed between the first electrode and the second electrode to cover an upper surface and a side surface of the first electrode and extending to the second region, and a second dielectric layer disposed between the second electrode and the third electrode to cover an upper surface and a side surface of the second electrode and extending to the third region and in contact with the first dielectric layer.

Claims (12)

1. A metal-insulator-metal capacitor, comprising:

N electrodes stacked on a substrate, where N is a plural integer, wherein each nth electrode covers an upper surface and a side surface of an n−1 electrode stacked therebelow, where n is an integer of 1 to N; and

M dielectric layers respectively interposed between the N electrodes, each mth dielectric layer covering upper surfaces and side surfaces of each nth electrode, where M=N−1 and m is an integer from 1 to M,

wherein a first dielectric layer among the M dielectric layers covers a top surface of the first electrode among the N electrodes, a side surface of the first electrode, and a top surface portion of the substrate adjacent the side surface of the first electrode,

wherein each of the second to Mth dielectric layers among the M dielectric layers covers the top surface of the respective second to N−1th electrodes, the side surface of the respective second to N−1th electrodes, and a top surface portion of the respective first to M−1 dielectric layers adjacent the side surface of the respective second to N−1th electrodes, wherein portions of the M dielectric layers extend parallel to the top surface of the substrate and are sequentially stacked over the top surface of the substrate to define a stack of parallel extending portions of the M dielectric layers, and

wherein one side region of the Nth electrode has a staircase structure with N−1 bent portions defining N−1 stairs of the staircase structure, and a bottom surface of a lowermost stair among the N−1 stairs is in direct contact with an uppermost surface of the stack of parallel extending portions of the M dielectric layers.

2. The metal-insulator-metal capacitor of claim 1 , wherein an interior angle between the upper surface and the side surface of each nth electrode is in a range of 90° to 135°.

3. The metal-insulator-metal capacitor of claim 2 , wherein an interior angle between the upper surface and the side surface of each nth electrode and an interior angle between the upper surface and the side surface of each n−1th electrode have an angle difference of 0° to 10°.

4. The metal-insulator-metal capacitor of claim 1 , wherein one side region of each nth electrode has a staircase structure with n−1 bent portions defining n−1 stairs of the staircase structure.

5. The metal-insulator-metal capacitor of claim 1 , wherein each of the first to n−1th dielectric layers has a uniform thickness.

6. The metal-insulator-metal capacitor of claim 5 , wherein the first to N−1th bent portions are formed in a staircase shape with a equal difference therebetween.

7. The metal-insulator-metal capacitor of claim 1 , wherein each nth electrode has at least one groove portion in which each mth dielectric layer is disposed on a bottom surface thereof in a region overlapping each n−1th electrode.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2022
From: KIM, JIHYUNG; AHN, JEONGHOON; OH, JAEHEE; DING, SHAOFENG; PARK, WONJI; HWANG, JEGWAN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 058662/0211 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2021
From: KIM, JIHYUNG; AHN, JEONGHOON; OH, JAEHEE; DING, SHAOFENG; PARK, WONJI; HWANG, JEGWAN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 058602/0067 →
Priority Claims (1)
KR 10-2021-0066797 · May 25, 2021 · national
Continuity (1)
Related Publication 20220384563A1 · Dec 1, 2022