Non-volatile memory device including selection gate and manufacturing method thereof

1. A non-volatile memory device, comprising:

a source region and a drain region disposed in a channel length direction on a substrate;

a flash cell, comprising a floating gate and a control gate, disposed between the source region and the drain region;

a selection gate disposed between the source region and the flash cell;

a selection line connecting the selection gate;

a word line connecting the control gate;

a common source line connected to the source region;

a bit line connected to the drain region;

a control gate pick up structure, connected to the control gate, comprising a plurality of floating gate poly-silicon patterns; and

a control gate contact plug disposed between the plurality of floating gate poly-silicon patterns.

2. The non-volatile memory device of claim 1 ,

wherein a length of the selection gate is longer than a length of the floating gate, based on a direction orthogonal to the channel length direction, and

wherein the length of the floating gate is shorter than a length of the control gate, based on the direction orthogonal to the channel length direction.

3. The non-volatile memory device of claim 1 , further comprising:

an extended selection gate connected to the selection gate; and

a selection gate contact plug disposed in the extended selection gate.

4. The non-volatile memory device of claim 3 ,

wherein a horizontal width of the extended selection gate is wider than a horizontal width of the selection gate.

5. The non-volatile memory device of claim 1 ,

wherein a spacer of the control gate and a spacer of the selection gate are spaced apart or in contact with each other.

6. The non-volatile memory device of claim 1 ,

wherein the selection gate is disposed lower than the floating gate or the control gate, relative to a surface of the substrate.

7. The non-volatile memory device of claim 1 ,

wherein the selection line and the word line are in parallel with each other,

wherein the common source line and the bit line are in parallel with each other, and

wherein the selection line and the word line are orthogonal to the common source line and the bit line, respectively.

8. The non-volatile memory device of claim 1 , further comprising:

a low concentration doping region disposed between the flash cell and the selection gate.

9. The non-volatile memory device of claim 1 ,

wherein floating gates are disposed in the control gate from a top view of the non-volatile memory device.

10. A non-volatile memory device, comprising:

a source region and a drain region disposed in a channel length direction on a substrate;

a flash cell, comprising a floating gate and a control gate, disposed between the source region and the drain region;

a selection gate disposed between the source region and the flash cell;

an extended selection gate extending from the selection gate; and

a control gate pick up structure, connected to the control gate, comprising floating gate poly-silicon patterns; and

a control gate contact plug disposed between the floating gate poly-silicon patterns.

11. The non-volatile memory device of claim 10 ,

wherein the control gate includes a first control gate and a second control gate,

wherein the first control gate and the second control gate are connected to each other and disposed to surround the floating gate, and

wherein widths of the first control gate and the second control gate are identical to each other.

12. The non-volatile memory device of claim 10 , further comprising:

a floating gate insulating film disposed between the substrate and the floating gate;

a control gate insulating film disposed between the substrate and the control gate; and

a selection gate insulating film disposed between the substrate and the selection gate.

13. The non-volatile memory device of claim 10 , further comprising

a selection gate contact plug disposed in the extended selection gate.

14. The non-volatile memory device of claim 10 , further comprising:

a control gate spacer disposed on a side of the control gate; and

a selection gate spacer disposed on a side of the selection gate.

15. The non-volatile memory device of claim 14 ,

wherein the control gate spacer and the selection gate spacer are spaced apart from each other.

16. The non-volatile memory device of claim 14 ,

wherein the control gate spacer and the selection gate spacer are in contact with each other.

17. The non-volatile memory device of claim 10 ,

wherein the selection gate is disposed lower than the floating gate or the control gate, relative to a surface of the substrate.

18. The non-volatile memory device of claim 10 ,

wherein a length of the selection gate is longer than a length of the floating gate, based on a direction orthogonal to the channel length direction, and

wherein the length of the floating gate is shorter than a length of the control gate, based on the direction orthogonal to the channel length direction.

19. A non-volatile memory device, comprising:

trenches disposed in a substrate;

a first source region and a first drain region disposed between a first trench of the trenches and a second trench of the trenches;

a second source region and a second drain region disposed between the second trench and a third trench of the trenches;

a flash cell comprising a floating gate, and a first control gate and a second control gate disposed on opposing sides of the floating gate, respectively, wherein the flash cell is disposed between the first source region and the first drain region;

a selection gate disposed between the source region and the flash cell; and

a logic gate disposed between the second source region and the second drain region,

wherein a length of the selection gate is longer than a length of the floating gate, and

wherein the length of the floating gate is shorter than a length of the control gate.

20. The non-volatile memory device of claim 19 , further comprising a well region, disposed below the logic gate, between the second trench and the third trench.