Method of manufacturing a magnetoresistive random access memory (MRAM)
The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared as follows: A single-crystalline MgO (001) substrate is prepared. An epitaxial Fe(001) lower electrode (a first electrode) is grown on a MgO(001) seed layer at room temperature, followed by annealing under ultrahigh vacuum. A MgO(001) barrier layer is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) is then formed on the MgO(001) barrier layer at room temperature. This is successively followed by the deposition of a Co layer on the Fe(001) upper electrode (the second electrode). The Co layer is provided so as to increase the coercive force of the upper electrode in order to realize an antiparallel magnetization alignment.
1. A magnetoresistive device comprising a magnetic tunnel junction structure comprising:
a tunnel barrier layer;
a first ferromagnetic material layer of the BCC structure formed on a first side of said tunnel barrier layer; and
a second ferromagnetic material layer of the BCC structure formed on a second side of said tunnel barrier layer,
wherein said tunnel barrier layer is formed by a single-crystalline MgOx (001) layer or a poly-crystalline MgOx (0<x<1) layer in which the (001) crystal plane is preferentially oriented.
2. A memory device comprising:
a transistor; and
the magnetoresistive device according to claim 1 , wherein said magnetoresistive device is used as a load for said transistor.
3. The magnetoresistive device of claim 1 , wherein 0.9<x<1.
4. The magnetoresistive device of claim 3 , wherein 0.98<x<1.
5. The magnetoresistive device of claim 4 , wherein 0.99<x<1.
6. The memory device of claim 2 , wherein 0.9<x<1.
7. The memory device of claim 6 , wherein 0.98<x<1.
8. The memory device of claim 7 , wherein 0.99<x<1.