IP Library › Granted Patent US 12,224,553
Granted Patent B2
US 12,224,553 · App. 17/561,212 · Granted Feb 11, 2025

Laser diode and manufacturing method of the same

Inventors: Su Hwan Oh (Daejeon, KR); Oh Kee Kwon (Sejong-si, KR); Chul-Wook Lee (Daejeon, KR); Kisoo Kim (Daejeon, KR)
Assignee: Electronics and Telecommunications Research Institute
H01S5/02461H01S5/0203H01S5/0207H01S5/024H01S5/0261H01S5/0268H01S5/06256H01S5/125
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Quick Facts
Patent No.
US 12,224,553
App. No.
17/561,212
Granted
Feb 11, 2025
Kind
B2
Abstract

Provided is a laser diode and a method for manufacturing the same. The diode includes a substrate including a DBR region having a channel hole, an active region, and a phase shift region, an optical waveguide provided on the substrate and extending from the active region to the DBR region, a lower insulation layer disposed on the optical waveguide, upper electrodes disposed on the lower insulation layer, and a heat blocking layer disposed in the channel hole of the DBR region and thermally separating the optical waveguide from the substrate.

Claims (33)

1. A laser diode comprising:

a substrate including an active region, a phase shift region adjacent to the active region, and a DBR region adjacent to the phase shift region and having a channel hole;

a lower clad layer disposed on the substrate;

an optical waveguide disposed on the lower clad layer and extending from the active region to the DBR region;

an upper clad layer disposed on the optical waveguide and the lower clad layer;

a lower insulation layer disposed on the lower clad layer, the upper clad layer, and the substrate of the phase shift region and the DBR region;

an upper insulation layer disposed on the lower insulation layer;

upper electrodes disposed on the upper insulation layer; and

a heat blocking layer disposed between the upper insulation layer and the lower insulation layer outside the lower clad layer, the optical waveguide, and the upper clad layer, the heat blocking layer disposed in the channel hole to thermally separate the optical waveguide from the substrate.

2. The laser diode of claim 1 , wherein the heat blocking layer comprises benzocyclbutene (BCB), or polyimide.

3. The laser diode of claim 1 , wherein the heat blocking layer has an M shape.

4. The laser diode of claim 1 , wherein the heat blocking layer is disposed on both sidewalls and a lower portion of the optical waveguide.

5. The laser diode of claim 1 , wherein the upper clad layer comprises a Bragg grating disposed in the DBR region.

6. The laser diode of claim 1 , wherein the lower insulation layer and the upper insulation layer comprise silicon nitride.

7. The laser diode of claim 1 , further comprising:

an ohmic electrode provided between the upper clad layer of the active region and one of the upper electrodes; and

electrode pads connected to the upper electrodes.

8. The laser diode of claim 7 , further comprising a pad insulation layer between one of the electrode pads of the active region and the substrate,

wherein the pad insulation layer includes benzocyclbutene (BCB), or polyimide.

9. The laser diode of claim 1 , further comprising a barrier layer between an inner wall of the channel hole and the heat blocking layer.

10. The laser diode of claim 1 , further comprising a lower electrode disposed on a lower surface of the substrate of the active region.

11. A method for manufacturing a laser diode, the method comprising:

forming a lower clad layer, an optical waveguide, and an upper clad layer on a substrate including an active region, a phase shift region, and a DBR region;

forming a lower insulation layer on the lower clad layer, the optical waveguide, the upper clad layer, and the substrate of the DBR region;

partially etching the lower insulation layer and the substrate outside the lower clad layer, the optical waveguide, and the upper clad layer of the phase shift region and the DBR region to form trenches;

etching the substrate on inner walls of the trenches to form a channel hole connecting the trenches;

forming a heat blocking layer inside of the channel hole and on the lower insulation layer;

forming an upper insulation layer on the heat blocking layer and on the lower insulation layer; and

forming upper electrodes on the upper insulation layer of the phase shift region and the DBR region, and on the upper clad layer of the active region.

12. The method of claim 11 , further comprising forming a contact electrode on the upper clad layer of the active region.

13. The method of claim 11 , further comprising forming a barrier layer on an inner wall of the channel hole.

14. The method of claim 11 , wherein the trenches are formed by a dry etching process.

15. The method of claim 11 , wherein the channel hole is formed by a wet etching process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 23, 2021
From: OH, SU HWAN; KWON, OH KEE; LEE, CHUL-WOOK; KIM, KISOO
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
Reel/Frame 058574/0758 →
Priority Claims (1)
KR 10-2021-0018253 · Feb 9, 2021 · national
Continuity (1)
Related Publication 20220255291A1 · Aug 11, 2022
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