IP Library › Granted Patent US 12,425,150
Granted Patent B2
US 12,425,150 · App. 17/561,738 · Granted Sep 23, 2025

Ultra-low latency PHY/MAC design for IEEE 802.11

Inventors: Minyoung Park (San Ramon, CA); Dave Cavalcanti (Portland, OR); Juan Fang (Portland, OR)
Assignee: INTEL CORPORATION
H04L5/0044H04L5/0082H04L27/26025H04L27/2634H04W84/12
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Quick Facts
Patent No.
US 12,425,150
App. No.
17/561,738
Granted
Sep 23, 2025
Kind
B2
Abstract

Provided herein is ultra-low latency (ULL) PHY/MAC design for IEEE 802.11. The disclosure provides an apparatus, comprising: interface circuitry; and processor circuitry coupled with the interface circuitry, wherein the processor circuitry is to: encode a ULL packet; and cause transmission of the ULL packet to an Access Point (AP) via the interface circuitry in an unlicensed spectrum, wherein a duration of the ULL packet is less than 20 microseconds. Other embodiments may also be disclosed and claimed.

Claims (38)

1. An apparatus, comprising:

interface circuitry; and

processor circuitry coupled with the interface circuitry,

wherein the processor circuitry is to:

encode an ultra-low latency (ULL) packet; and

cause transmission of the ULL packet to an Access Point (AP) via the interface circuitry in an unlicensed spectrum,

wherein a duration of the ULL packet is less than 20 microseconds, and

wherein an Orthogonal Frequency Division Multiplexing (OFDM) symbol duration for the ULL packet is less than 3.2 microseconds.

2. The apparatus of claim 1 , wherein the ULL packet excludes a legacy preamble of an Institute of Electrical and Electronic Engineers (IEEE) 802.11ax packet or a before-IEEE 802.11ax packet.

3. The apparatus of claim 1 , wherein the processor circuitry is to:

cause transmission of the ULL packet to the AP across a wide band.

4. The apparatus of claim 3 , wherein the wide band includes an 80 MHz or 160 MHz band.

5. The apparatus of claim 1 , wherein a subcarrier frequency spacing for the ULL packet is greater than 312.5 kHz.

6. The apparatus of claim 5 , wherein the subcarrier frequency spacing includes 1.25 MHz or 2.5 MHz.

7. The apparatus of claim 1 , wherein an Inverse Discrete Fourier Transformation (IDFT)/Discrete Fourier Transformation (DFT) period for the ULL packet includes 0.8 microseconds or 0.4 microseconds.

8. The apparatus of claim 1 , wherein a guard interval duration for the ULL packet includes 0.8 microseconds or 0.4 microseconds.

9. The apparatus of claim 1 , wherein the OFDM symbol duration includes 1.6 microseconds or 0.8 microseconds.

10. The apparatus of claim 1 , wherein a duration of a short-training field for the ULL packet is less than 4 microseconds.

11. The apparatus of claim 10 , wherein the duration of the short-training field includes 2 microseconds or 1 microsecond.

12. The apparatus of claim 1 , wherein a duration of a long-training field for the ULL packet is less than 4 microseconds.

13. The apparatus of claim 12 , wherein the duration of the long-training field includes 2.4 microseconds or 1.2 microsecond.

14. The apparatus of claim 1 , wherein a signal field for the ULL packet includes 2 Orthogonal Frequency Division Multiplexing (OFDM) symbols.

15. The apparatus of claim 1 , wherein a duration of a preamble of the ULL packet is less than a duration of a legacy preamble of an Institute of Electrical and Electronic Engineers (IEEE) 802.11ax packet or a before-IEEE 802.11ax packet.

16. The apparatus of claim 15 , wherein the duration of the preamble of the ULL packet includes 7.6 microseconds or 3.8 microsecond.

17. The apparatus of claim 1 , wherein the processor circuitry is to:

encode the ULL packet with dual-carrier modulation or quad-carrier modulation.

18. The apparatus of claim 1 , wherein the processor circuitry is to:

cause transmission of the ULL packet to the AP when there is an ongoing transmission from an Overlapping Basic Service Set (OBSS) network.

19. The apparatus of claim 1 , wherein the processor circuitry is to identify the ULL packet via:

a higher layer packet classification tag;

a Media Access Control (MAC) layer traffic flow identifier (ID); or

a dedicated traffic identifier (TID).

20. The apparatus of claim 1 , wherein the processor circuitry is to:

cause transmission of the ULL packet to the AP over 6 GHz band.

21. The apparatus of claim 1 , wherein the processor circuitry is to:

encode the ULL packet with 64 tones or 128 tones.

22. The apparatus of claim 1 , wherein a size of the ULL packet is equal to or less than a predefined packet size threshold.

23. The apparatus of claim 1 , wherein a duration of the ULL packet is equal to or less than a predefined packet duration threshold.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2026
From: INTEL CORPORATION
To: INTEL PRODUCTS IP LLC
Reel/Frame 076091/0202 →
Continuity (1)
Related Publication 20220173853A1 · Jun 2, 2022
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