Granted Patent B2

US 12,506,568 · App. 17/561,740 · Granted Dec 23, 2025

Inventors: Dave Cavalcanti (Portland, OR); Juan Fang (Portland, OR); Mikhail Galeev (Beaverton, OR); Javier Perez-Ramirez (North Plains, OR); Laurent Cariou (Milizac, FR); Alexander Min (Portland, OR)

Assignee: INTEL CORPORATION

H04L5/0007H04L1/0003H04L1/0009H04L5/0048

Abstract

Claims (72)

1 . An apparatus, comprising:

interface circuitry; and

processor circuitry coupled with the interface circuitry,

wherein the processor circuitry is to:

encode a Preemptable Physical Protocol Data Unit (P-PPDU) packet; and

cause transmission of the P-PPDU packet to multiple Stations (STAs) from an Access Point (AP) via the interface circuitry,

wherein the P-PPDU packet includes a plurality of Media Access Control (MAC) Protocol Data Unit (MPDU) segments of an Aggregated MPDU (A-MPDU), each MPDU segment includes one or more MPDUs, and wherein the P-PPDU packet includes a midamble (MA) for each MPDU segment,

wherein the P-PPDU packet is associated with the multiple STAs based on Orthogonal Frequency-Division Multiple Access (OFDMA), each of the multiple STAs is assign with a respective resource unit (RU) in frequency domain, and the P-PPDU packet further includes a single Wideband MA (WMA) for the multiple STAs across the P-PPDU packet in the frequency domain,

wherein the processor circuitry is further to:

postpone the transmission of the P-PPDU packet when time-sensitive traffic arrives;

insert the time-sensitive traffic after the WMA for transmission to a requesting STA of the time-sensitive traffic via the interface circuitry, wherein the WMA indicates that the P-PPDU packet will be preemptied by the time-sensitive traffic, and the WMA further indicates a new resource allocation for transmission of subsequent part of the P-PPDU packet for the multiple STAs after the transmission of the time-sensitive traffic is completed; and

resume, after the transmission of the time-sensitive traffic is completed, the transmission of the subsequent part of the P-PPDU packet to the multiple STAs based on the new resource allocation.

2 . The apparatus of claim 1 , wherein the processor circuitry is further to:

decode a request from the requesting STA, the request includes a latency and reliability requirement for the time-sensitive traffic; and

schedule the postponing and inserting in response to the request.

3 . The apparatus of claim 1 , wherein the MA is to include:

a preemption field to indicate a type of a preemption;

a STA Identifier (ID) field to indicate a STA for which a MPDU segment associated with the MA is assigned;

a segment length field to indicate a length of a MPDU segment associated with the MA;

a Modulation and Coding Scheme (MCS) field to indicate a coding and modulation scheme for a MPDU segment associated with the MA;

a padding field to indicate padding before insertion of a Wideband MA (WMA);

a Cyclic Redundancy Check (CRC) field to detect decoding error;

a Binary Convolutional Codes (BCC) padding field to flush BCC; or

a delimiter signature field to detect presence of the MA.

4 . The apparatus of claim 3 , wherein the MPDU segment associated with the MA includes either the time-sensitive traffic or non-time-sensitive traffic.

5 . The apparatus of claim 1 , wherein the MA is to include a preemption field to indicate a type of a preemption, wherein the type of the preemption includes a RU based preemption or a wideband based preemption.

6 . The apparatus of claim 1 , wherein the P-PPDU packet includes multiple A-MPDUs, and wherein each of the multiple STAs is associated with a respective one of the multiple A-MPDUs.

7 . The apparatus of claim 1 , wherein the WMA is associated with one or more STAs.

8 . The apparatus of claim 1 , wherein the WMA is to include:

a training field to allow a STA to perform wideband channel estimation;

a user information field to indicate a RU allocation, a coding and modulation scheme, or a frame length for a MPDU segment associated with the WMA;

a maximum segment length field to indicate a maximum length among MPDU segments associated with the WMA;

a Modulation and Coding Scheme (MCS) field to indicate a coding and modulation scheme for a MPDU segment associated with the WMA;

a Cyclic Redundancy Check (CRC) field to detect decoding error; or

a Binary Convolutional Codes (BCC) padding field to indicate padding bits required to flush BCC.

9 . The apparatus of claim 8 , wherein the MPDU segment associated with the WMA includes the time-sensitive traffic.

10 . The apparatus of claim 1 , wherein the processor circuitry includes a MAC logic and a Physical (PHY) logic,

wherein the MAC logic is to:

arrange a time-sensitive frame into a queue;

provide, when the time-sensitive frame is ready for transmission and the P-PPDU packet is ongoing, the time-sensitive frame as a parameter to the PHY logic via a dedicated primitive, and

wherein the PHY logic is to:

preempt the P-PPDU packet to insert the time-sensitive frame.

11 . An apparatus, comprising:

interface circuitry; and

processor circuitry coupled with the interface circuitry,

wherein the processor circuitry is to:

decode a Preemptable Physical Protocol Data Unit (P-PPDU) packet received from an Access Point (AP) via the interface circuitry, wherein the P-PPDU packet includes a plurality of Media Access Control (MAC) Protocol Data Unit (MPDU) segments of an Aggregated MPDU (A-MPDU), each MPDU segment includes one or more MPDUs, and wherein the P-PPDU packet includes a midamble (MA) for each MPDU segment; and

determine, based on the MA, a target Station (STA) of a MPDU segment associated with the MA,

wherein the P-PPDU packet is associated with multiple STAs based on Orthogonal Frequency-Division Multiple Access (OFDMA), each of the multiple STAs is assign with a respective resource unit (RU) in frequency domain, and the P-PPDU packet further includes a single Wideband MA (WMA) for the multiple STAs across the P-PPDU packet in the frequency domain, and

wherein the WMA indicates that the P-PPDU packet will be preemptied by time-sensitive traffic, and the WMA further indicates a new resource allocation for transmission of subsequent part of the P-PPDU packet for the multiple STAs after transmission of the time-sensitive traffic is completed, and

wherein the processor circuitry is to:

postpone the decoding of the P-PPDU packet according to the WMA; and

resume, after the transmission of the time-sensitive traffic is completed, the decoding of the subsequent part of the P-PPDU packet based on the new resource allocation.

12 . The apparatus of claim 11 , wherein the processor circuitry is further to:

encode a request for time-sensitive traffic;

cause transmission of the request to the AP via the interface circuitry; and

decode, in response to the request, the P-PPDU packet for the time-sensitive traffic.

13 . The apparatus of claim 12 , wherein the MPDU segment associated with the MA includes the time-sensitive traffic.

14 . The apparatus of claim 11 , wherein the processor circuitry is further to:

pause processing of the P-PPDU packet when the MA indicates that the MPDU segment associated with the MA includes the time-sensitive traffic.

15 . The apparatus of claim 11 , wherein the MA is to include:

a preemption field to indicate a type of a preemption;

a STA Identifier (ID) field to indicate a STA for which a MPDU segment associated with the MA is assigned;

a segment length field to indicate a length of a MPDU segment associated with the MA;

a Modulation and Coding Scheme (MCS) field to indicate a coding and modulation scheme for a MPDU segment associated with the MA;

a padding field to indicate padding before insertion of a Wideband MA (WMA);

a Cyclic Redundancy Check (CRC) field to detect decoding error;

a Binary Convolutional Codes (BCC) padding field to flush BCC; or

a delimiter signature field to detect presence of the MA.

16 . The apparatus of claim 11 , wherein the MPDU segment associated with the MA includes either the time-sensitive traffic or non-time-sensitive traffic.

17 . The apparatus of claim 11 , wherein the MA is to include a preemption field to indicate a type of a preemption, wherein the type of the preemption includes a RU based preemption or a wideband based preemption.

18 . The apparatus of claim 11 , wherein the P-PPDU packet includes multiple A-MPDUs, and wherein each of the multiple STAs is associated with a respective one of the multiple A-MPDUs.

Assignments (2)

Continuity (1)

References Cited (10)