Circuit interconnect structure
One or more systems, devices and/or methods provided herein relate to a circuit device having a modular or selectively designed interconnect structure with a plurality of conformal features. In the semiconductor realm, such achievements can allow for fabrication of a device with sub 18 nanometer (nm) or lesser pitch between adjacent and/or parallel lines of the interconnect structure. A device can comprise a semiconductor device having an interconnect structure having a first set of parallel lines and a second set of parallel lines, where the lines of the first set can be arranged in a transverse direction to the lines of the second set. The lines of the first set can be disposed orthogonally to the lines of the second set. The first second sets of lines can comprise first and second rounded jogs that are conformal to one another and which connect the first set of lines to the second set of lines.
1. A method, comprising:
forming, by self-aligned quadruple patterning (SAQP), by a system operatively coupled to a processor, an interconnect structure of a semiconductor device, the interconnect structure having a first set of parallel lines and a second set of parallel lines, wherein the parallel lines of the first set are arranged in a transverse direction to the parallel lines of the second set, wherein the forming comprises:
applying, by the system, a conformal spacer about a mandrel having first and second portions transverse to one another, and
removing, by the system, the mandrel to form the first set of parallel lines and the second set of parallel lines comprising a rounded jog connecting one line of the first set and one line of the second set.
2. The method of claim 1 , wherein the forming comprises:
forming, by the system, the parallel lines of the first set are disposed orthogonally to the parallel lines of the second set.
3. The method of claim 1 , wherein the forming comprises:
forming, by the system, the parallel lines of the first set at a first pitch of 18 nanometers or less; and
forming, by the system, the parallel lines of the second set at a second pitch of 18 nanometers or less.
4. The method of claim 1 , wherein the forming comprises:
using, by the system, one or more comb-shaped mandrels.
5. The method of claim 1 , wherein the first set of parallel lines and the second set of parallel lines together define a comb-serpentine structure.
6. The method of claim 1 , further comprising forming a set of vias connected across the interconnect structure.
7. The method of claim 5 , wherein the rounded jog is a first rounded jog, and wherein the forming further comprises:
applying, by the system, another conformal spacer about the first set of parallel lines and the second set of parallel lines; and
removing, by the system, the another conformal spacer to at least in part form the first set of parallel lines and the second set of parallel lines comprising comprise the first rounded jog and a second rounded jog that are conformal to one another and which connect the first set of parallel lines to the second set of parallel lines.
8. A device, comprising:
a semiconductor device having an interconnect structure, wherein the interconnect structure comprises a first set of parallel lines and a second set of parallel lines, and wherein the parallel lines of the first set are arranged in a transverse direction to the parallel lines of the second set, wherein the first set of parallel lines and the second set of parallel lines comprise a rounded jog connecting one line of the first set and one line of the second set.
9. The device of claim 8 , wherein the parallel lines of the first set are disposed orthogonally to the parallel lines of the second set.
10. The device of claim 8 , wherein the parallel lines of the first set are arranged a first pitch of 18 nanometers or less, and wherein the parallel lines of the second set are arranged a second pitch of 18nanometers or less.
11. The device of claim 8 , wherein the rounded jog is a first rounded jog, and wherein the first set of parallel lines and the second set of parallel lines comprise the first rounded jog and a second rounded jog that are conformal to one another and which connect the first set of parallel lines to the second set of parallel lines.
12. The device of claim 8 , wherein the first set of parallel lines and the second set of parallel lines together define a comb-serpentine structure.
13. The device of claim 8 , further comprising:
a plurality of disconnected sections of the interconnect structure that are disconnected from one another.
14. A system, comprising:
a semiconductor device comprising a circuit, wherein the circuit comprises:
an interconnect structure having a first set of parallel lines and a second set of parallel lines, wherein the parallel lines of the first set are arranged in a transverse direction to the parallel lines of the second set, wherein the first set of parallel lines and the second set of parallel lines comprise a rounded jog connecting one line of the first set and one line of the second set; and
a set of vias connected across the interconnect structure.
15. The system of claim 14 , wherein the parallel lines of the first set are disposed orthogonally to the parallel lines of the second set.
16. The system of claim 14 , wherein the parallel lines of the first set are arranged a first pitch of 18 nanometers or less, and wherein the parallel lines of the second set are arranged a second pitch of 18 nanometers or less.
17. The system of claim 14 , wherein the rounded jog is a first rounded jog, and wherein the first set of parallel lines and the second set of parallel lines comprise the first rounded jog and a second rounded jog that are conformal to one another and which connect the first set of parallel lines to the second set of parallel lines.
18. The system of claim 14 , further comprising:
the set of vias electrically connected to the interconnect structure and vias of the set of vias electrically connected to one another across disconnected sections of the interconnect structure.
19. The system of claim 14 , further comprising:
the semiconductor device having a charge applied across disconnected sections of the interconnect structure via the set of vias.
20. The system of claim 14 , wherein the first set of parallel lines and the second set of parallel lines together define a comb-serpentine structure.