High voltage semiconductor device with ESD self-protection capability and manufacturing method thereof
A semiconductor device includes a P-type body region and an N-type drift region disposed in a substrate; a gate electrode, disposed on the P-type body region and the N-type drift region, including a high concentration doping region and a high resistance region, wherein a dopant concentration of the high concentration doping region is higher than a dopant concentration of the high resistance region; a spacer disposed on a side of the gate electrode; a highly doped source region disposed in the P-type body region; and a highly doped drain region disposed in the N-type body region. The high concentration doping region overlaps the P-type body region, and the high resistance region overlaps the N-type drift region.
1. A semiconductor device, comprising:
a P-type body region and an N-type drift region disposed in a substrate;
a gate electrode disposed on the P-type body region and the N-type drift region and comprising a high concentration doping region and a high resistance region, wherein a dopant concentration of the high concentration doping region is higher than a dopant concentration of the high resistance region;
a gate silicide film formed adjacent to a silicide blocking insulating film and disposed on the gate electrode so as to vertically overlap the high concentration doping region and the high resistance region,
wherein the gate silicide film is formed on an entire upper surface of the high concentration doping region and a portion of an upper surface of the high resistance region, such that the high resistance region passes through an interface between the gate silicide film and the silicide blocking insulating film and extends to an interface between the high concentration doping region and the high resistance region;
a highly doped source region disposed in the P-type body region;
a highly doped drain region disposed in the N-type drift region;
a first spacer on one sidewall of the gate electrode and adjacent to the highly doped source region, and a second spacer on the other sidewall of the gate electrode and adjacent to the highly doped drain region,
wherein the silicide blocking insulating film comprises a first portion on an upper surface of the gate electrode, a second portion on the second spacer, and a third portion on the N-type drift region and in direct contact with a gate insulating film;
a P-type buried layer abutting the P-type body region, having a different dopant concentration than the P-type body region, and disposed below the N-type drift region; and
an N-type buried layer disposed below the P-type buried layer and the P-type body region,
wherein the gate silicide film vertically overlaps the P-type body region, the N-type drift region and the P-type buried layer,
wherein the high concentration doping region is in contact with the P-type body region and the N-type drift region via the gate insulating film, and the high resistance region is in contact with the N-type drift region via the gate insulating film, and
wherein the interface between the high concentration doping region and the high resistance region is spaced apart from the interface between the gate silicide film and the silicide blocking insulating film.
2. The semiconductor device of claim 1 , wherein the gate silicide film is in contact with the high concentration doping region and the high resistance region.
3. The semiconductor device of claim 1 , further comprising:
a deep trench structure disposed on each opposite side of the N-type buried layer.
4. The semiconductor device of claim 1 , wherein the high resistance region is a low concentration doping region or an undoped region.
5. The semiconductor device of claim 1 , wherein the high concentration doping region is closer to the highly doped source region than the highly doped drain region,
wherein the high resistance region is closer to the highly doped drain region than the highly doped source region, and
wherein a concentration of the high concentration doping region is similar to a concentration of either the highly doped source region or the highly doped drain region.
6. The semiconductor device of claim 1 ,
wherein the silicide blocking insulating film is disposed to extend from the interface surface of the gate electrode to partially overlap the highly doped drain region,
wherein the silicide blocking insulating film contacts the high resistance region, and
wherein the high resistance region contacts the gate silicide film, the gate insulating film, and the silicide blocking insulating film.
7. The semiconductor device of claim 1 , wherein a vertical boundary between the P-type body region and the P-type buried layer is spaced apart from the interface between the gate silicide film and the silicide blocking insulating film.
8. The semiconductor device of claim 1 , wherein the interface between the high concentration doping region and the high resistance region is spaced apart from a vertical boundary between the P-type body region and the N-type drift region.
9. The semiconductor device of claim 1 , further comprising:
a drain silicide layer disposed on the highly doped drain region,
wherein the third portion of the silicide blocking insulating film is disposed on the highly doped drain region and is adjacent to the drain silicide layer.
10. The semiconductor device of claim 1 , wherein the gate insulating film is in contact with the high concentration doping region, the high resistance region, the P-type body region, the N-type drift region, the first spacer, the second spacer, and the third portion of the silicide blocking insulating film, respectively.
11. A semiconductor device, comprising:
a gate electrode disposed on a P-type body region and an N-type drift region and comprising a high concentration doping region and a high resistance region, wherein a dopant concentration in the high concentration doping region and a dopant concentration in the high resistance region are different;
a gate silicide film formed adjacent to a silicide blocking insulating film and disposed on the gate electrode so as to vertically overlap the high concentration doping region and the high resistance region,
wherein the gate silicide film is formed on an entire upper surface of the high concentration doping region and a portion of an upper surface of the high resistance region, such that the high resistance region passes through an interface between the gate silicide film and the silicide blocking insulating film and extends to an interface between the high concentration doping region and the high resistance region;
a highly doped source region disposed in the P-type body region;
a highly doped drain region disposed in the N-type drift region;
a first spacer on one sidewall of the gate electrode and adjacent to the highly doped source region, and a second spacer on the other sidewall of the gate electrode and adjacent to the highly doped drain region,
wherein the silicide blocking insulating film comprises a first portion on an upper surface of the gate electrode, a second portion on the second spacer, and a third portion on the N-type drift region and in direct contact with a gate insulating film;
a P-type buried layer abutting the P-type body region, having a different dopant concentration than the P-type body region, and disposed below the N-type drift region; and
an N-type buried layer disposed below the P-type buried layer and the P-type body region,
wherein the gate silicide film vertically overlaps the P-type body region, the N-type drift region, and the P-type buried layer,
wherein the high concentration doping region is in contact with the P-type body region and the N-type drift region via the gate insulating film, and the high resistance region is in contact with the N-type drift region via the gate insulating film, and
wherein the interface between the high concentration doping region and the high resistance region is spaced apart from the interface between the gate silicide film and the silicide blocking insulating film.
12. The semiconductor device of claim 11 , wherein the high resistance region is spaced apart from the highly doped drain region.
13. The semiconductor device of claim 11 , wherein a vertical boundary between the P-type body region and the P-type buried layer is spaced apart from the interface between the gate silicide film and the silicide blocking insulating film.
14. The semiconductor device of claim 11 , wherein the interface between the high concentration doping region and the high resistance region is spaced apart from a vertical boundary between the P-type body region and the N-type drift region.
15. The semiconductor device of claim 11 , further comprising:
a drain silicide layer disposed on the highly doped drain region,
wherein the third portion of the silicide blocking insulating film is disposed on the highly doped drain region and is adjacent to the drain silicide layer.
16. The semiconductor device of claim 11 , wherein the gate insulating film is in contact with the high concentration doping region, the high resistance region, the P-type body region, the N-type drift region, the first spacer, the second spacer, and the third portion of the silicide blocking insulating film, respectively.