Rational ratio multiplier (RRM) with optimized duty cycle implementation
Design and methods for implementing a Rational Ratio Multiplier (RRM) with close to 50% duty cycle. This invention gives an optimal way to implement an RRM that saves both area and power for a given design and is able to achieve a good accuracy of the output clock with a difference between the high period and the low period of the output clock by only half a cycle of the input clock which is the closest to get to a 50% duty cycle clock.
1. An apparatus comprising:
a Rational Ratio Multiplier (RRM) implementation comprising:
a first input to receive a first value N;
a second input to receive a second value D, wherein the value N and the value D provide a rational ratio fraction N/D while D>N of the RRM;
a counter, the counter configured to count from 1 to a sum of a high period value and a low period value, wherein the high period value is defined by a desired number of rising edges and falling edges of an input clock while an output clock is at a high clock period and the low period value is defined by a desired number of rising edges and falling edges of the input clock while the output clock is at a low clock period, wherein the low period value and the high period value are derived from the N value and the D value;
a first T-FF that samples at a rising edge of the input clock;
a second T-FF that samples at the rising edge of the input clock;
a third T-FF that samples at a falling edge of the input clock;
a fourth T-FF that samples at the falling edge of the input clock;
wherein the first T-FF, the second T-FF, the third T-FF, and the fourth T-FF are configured to toggle based a count of the counter;
a logic circuit configured to receive output signals of the first T-FF, the second T-FF, the third T-FF, and the fourth T-FF and generate from the output signals the output clock.
2. An apparatus of claim 1 , wherein the high period value is equal to the low period value when the N value is equal to 1, wherein the high period value is larger by 1 than the low period value when the N value is greater than 1.
3. An apparatus of claim 1 , wherein when the N value is not equal to 1, the logic circuit is configured to generate the output clock by a XOR function between one AND function of an output of the first T-FF and an output of the third T-FF with another AND function of an output of the second T-FF and an output of the fourth T-FF.
4. An apparatus of claim 1 , wherein when the N value is equal to 1, the logic circuit is configured to generate the output clock by a XOR function of an output of the first T-FF with an output of the fourth T-FF when the high period value is odd, and by a XOR function of the output of the first T-FF with an output of the second T-FF when the high period value is even.
5. The apparatus of claim 1 wherein:
the first T-FF includes a clock input configured to receive the input clock;
the second T-FF includes a clock input configured to receive the input clock;
the third T-FF includes a clock input configured to receive a second clock that is inverse to the input clock;
the fourth T-FF includes a clock input configured to receive the second clock.
6. An apparatus of claim 1 , wherein;
the first T-FF is configured to toggle when the count of the counter equals the high period value and when the count of the counter equals the sum of both the high period value and the low period value;
the second T-FF is configured to toggle when the count of the counter equals half of the high period value and when the count of the counter equals half of the sum of both the high period value and the low period value;
the third T-FF is configured to toggle when the count of the counter equals the high period value and when the count of the counter equals the sum of both the high period value and low period value;
the fourth T-FF is configured to toggle when the count of the counter equals half of the high period value+1 and when the count of the counter equals half of the low period value+1.