Compact transformer-based notch filter
A notch filter is coupled to a first input node and a second input node, and is configured to present a capacitive load to a differential signal provided to the first and second input nodes, and to present a series-resonant inductive-capacitive load to a common-mode signal provided to the first and second input nodes. The notch filter includes a transformer and a capacitor bank. The transformer includes a first winding having a positive-polarity terminal coupled to the first input node and a second winding having a positive-polarity terminal coupled to the second input node. The capacitor bank includes a first capacitor coupled between a negative-polarity terminal of the first winding and a bias node, and a second capacitor coupled between a negative-polarity terminal of the second winding and the bias node. The first and second capacitors may be variable capacitors.
1. A circuit comprising:
a first input node;
a second input node;
a bias voltage node coupled to a direct-current (DC) voltage value; and
a notch filter, the notch filter comprising:
a filter transformer including a first winding and a second winding, and
a capacitor bank including a first capacitor and a second capacitor,
wherein a positive-polarity terminal of the first winding is coupled to the first input node and a negative-polarity terminal of the first winding is coupled to a first terminal of the first capacitor;
wherein a positive-polarity terminal of the second winding is coupled to the second input node and a negative-polarity terminal of the second winding is coupled to a first terminal of the second capacitor, and
wherein a second terminal of the first capacitor and a second terminal of the second capacitor are coupled to the bias voltage node.
2. The circuit of claim 1 , wherein a ratio of a number of turns of the first winding to a number of turns of the second winding is 1-to-1.
3. The circuit of claim 1 , wherein a self-inductance of the first winding is substantially equal to a self-inductance of the second winding.
4. The circuit of claim 1 , wherein a self-inductance of the first winding is substantially equal to a mutual-inductance between the first winding and the second winding.
5. The circuit of claim 1 ,
wherein the first winding and the second winding are disposed within a semiconductor die, and
wherein an area occupied by the first winding overlaps an area occupied by the second winding.
6. The circuit of claim 5 , wherein the capacitor bank is disposed within the semiconductor die.
7. The circuit of claim 1 , wherein the bias voltage node is coupled to ground.
8. The circuit of claim 1 , wherein a capacitance of the first capacitor is equal to a capacitance of the second capacitor.
9. The circuit of claim 1 ,
wherein the first capacitor is a variable capacitor having a capacitance controlled by a capacitance control signal, and
wherein the second capacitor is a variable capacitor having a capacitance controlled by the capacitance control signal.
10. The circuit of claim 9 , wherein for each of a plurality of values of the capacitance control signal, a capacitance of the first capacitor corresponding to that value is equal to a capacitance of the second capacitor corresponding to that value.
11. The circuit of claim 1 , further comprising:
an output transformer including a primary winding and secondary winding,
wherein a first terminal of the primary winding is coupled to the first input node and a second terminal of the primary winding is coupled to the second input node.
12. The circuit of claim 11 ,
wherein the first input node is coupled to a positive output signal of a differential power amplifier, and
wherein the second input node is coupled to a negative output signal of the differential power amplifier.