Reference voltage generator based on threshold voltage difference of field effect transistors

1. A reference voltage generator, comprising:

a first field effect transistor (FET) including a first threshold voltage;

a second FET including a second threshold voltage different than the first threshold voltage;

a gate voltage generator coupled to gates of the first and second FETs;

a first current source coupled in series with the first FET between a first voltage rail and a second voltage rail;

a second current source, wherein the gate voltage generator comprises an operational amplifier including:

a first input coupled to a first node between the first current source and the first FET;

a second input coupled to a second node between the second current source and the second FET; and

an output coupled to the gates of the first and second FETs;

a first resistor coupled in series with the second current source and the second FET between the first and second voltage rails, wherein a reference voltage is generated across the first resistor; and

a second resistor coupled between the first node and the first FET.

2. The reference voltage generator of claim 1 , wherein the first and second resistors have substantially the same resistance.

3. The reference voltage generator of claim 1 , wherein the first and second current sources are coupled together to form a current mirror.

4. The reference voltage generator of claim 3 , wherein a current ratio of the current mirror is M over N, wherein M is different than N.

5. The reference voltage generator of claim 3 , wherein a current ratio of the current mirror is substantially one-to-one.

6. The reference voltage generator of claim 1 , wherein the gate voltage generator is configured to provide a gate voltage to the first and second FETs to operate the first and second FETs in sub-threshold region.

7. The reference voltage generator of claim 1 , wherein the first threshold voltage is greater than the second threshold voltage.

8. A reference voltage generator, comprising:

a first field effect transistor (FET) including a first threshold voltage;

a second FET including a second threshold voltage different than the first threshold voltage;

a gate voltage generator coupled to gates of the first and second FETs;

a first current source coupled in series with the first FET between a first voltage rail and a second voltage rail;

a second current source, wherein the first and second current sources comprise third and fourth FETs, respectively, and wherein gates of the third and fourth FETs are coupled together, and to a drain of the third FET; and

a first resistor coupled in series with the second current source and the second FET between the first and second voltage rails, wherein a reference voltage is generated across the first resistor.

9. The reference voltage generator of claim 8 , wherein the first and second FETs are each an n-channel metal oxide semiconductor (NMOS) FET, and wherein the third and fourth FETs are each a p-channel metal oxide semiconductor (PMOS) FET.

10. A reference voltage generator, comprising:

a first field effect transistor (FET) including a first threshold voltage;

a second FET including a second threshold voltage different than the first threshold voltage;

a gate voltage generator coupled to gates of the first and second FETs;

a first current source coupled in series with the first FET between a first voltage rail and a second voltage rail;

a second current source, wherein the first and second current sources comprise third and fourth FETs, respectively, wherein the first and second FETs are each a p-channel metal oxide semiconductor (PMOS) FET, and wherein the third and fourth FETs are each an n-channel metal oxide semiconductor (NMOS) FET; and

a first resistor coupled in series with the second current source and the second FET between the first and second voltage rails, wherein a reference voltage is generated across the first resistor.

11. A method of generating a reference voltage, comprising:

generating a first current through a first field effect transistor (FET) including a first threshold voltage;

generating a second current through a second FET including a second threshold voltage different than the first threshold voltage; and

routing the second current through a first resistor to generate the reference voltage across the first resistor, wherein the reference voltage is substantially temperature independent over a temperature range of around −40 degrees Celsius to 120 degrees Celsius.

12. The method of claim 11 , wherein the second threshold voltage is greater than the first threshold voltage.

13. The method of claim 11 , wherein the first current is substantially equal to the second current.

14. The method of claim 11 , wherein the first current is different than the second current.

15. The method of claim 11 , further comprising:

biasing the first FET with a first drain-to-source voltage; and

biasing the second FET with a second drain-to-source voltage, wherein the first drain-to-source voltage is substantially equal to the second drain-to-source voltage.

16. An apparatus for generating a reference voltage, comprising:

means for generating a first current through a first field effect transistor (FET) including a first threshold voltage;

means for generating a second current through a second FET including a second threshold voltage different than the first threshold voltage; and

means for routing the second current through a first resistor to generate the reference voltage across the first resistor, wherein the reference voltage is substantially temperature independent over a temperature range of around −40 degrees Celsius to 120 degrees Celsius.

17. The apparatus of claim 16 , wherein the second threshold voltage is greater than the first threshold voltage.

18. The apparatus of claim 16 , wherein the first current is substantially equal to the second current.

19. The apparatus of claim 16 , wherein the first current is different than the second current.

20. The apparatus of claim 16 , further comprising:

means for biasing the first FET with a first drain-to-source voltage; and

means for biasing the second FET with a second drain-to-source voltage, wherein the first drain-to-source voltage is substantially equal to the second drain-to-source voltage.

21. A wireless communication device, comprising:

one or more signal processing cores;

at least one antenna; and

a transceiver coupled to the one or more signal processing cores and to the at least one antenna, wherein the transceiver includes a reference voltage generator, comprising:

a first field effect transistor (FET) including a first threshold voltage;

a second FET including a second threshold voltage different than the first threshold voltage;

a gate voltage generator coupled to gates of the first and second FETs;

a first current source coupled in series with the first FET between a first voltage rail and a second voltage rail;

a second current source; and

a first resistor coupled in series with the second current source and the second FET between the first and second voltage rails, wherein a reference voltage is generated across the first resistor.

22. The wireless communication device of claim 21 , wherein the gate voltage generator comprises an operational amplifier including:

a first input coupled to a first node between the first current source and the first FET;

a second input coupled to a second node between the second current source and the second FET; and

an output coupled to the gates of the first and second FETs.

23. The wireless communication device of claim 22 , further comprising a second resistor coupled between the first node and the first FET.

24. The wireless communication device of claim 22 , wherein the first and second current sources are coupled together to form a current mirror.

25. The wireless communication device of claim 24 , wherein a current ratio of the current mirror is substantially one-to-one.