High connectivity device stacking
The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.
1. A semiconductor device assembly, comprising:
a semiconductor core structure, comprising:
a silicon core comprising a first core surface opposite a second core surface, the silicon core further comprising first via formed therein, the first via comprising a first via surface that defines a first opening extending through the silicon core from the first core surface to the second core surface;
an insulating layer disposed over the first core surface, the second core surface, and the first via surface; and
an electrical interconnection formed within the first via, the insulating layer disposed between the electrical interconnection and the via surface; and
a device spacer comprising:
a frame having a first frame surface opposite a second frame surface, the frame further comprising:
a frame material that comprises a polymer-based dielectric material having ceramic filler particles; and
a second via comprising a second via surface that defines a second opening extending through the frame from the first frame surface to the second frame surface;
an electrical interconnection disposed within the second via, the electrical interconnection disposed on the second via surface; and
a barrier layer lining the second via surface and disposed between the second via surface and the electrical interconnection.
2. The semiconductor device assembly of claim 1 , wherein the barrier layer comprises molybdenum.
3. The semiconductor device assembly of claim 1 , wherein the insulating layer comprises an epoxy resin material.
4. The semiconductor device assembly of claim 1 , further comprising:
a passivating layer disposed between the silicon core and the insulating layer, the passivating layer comprising an oxide material.
5. The semiconductor device assembly of claim 1 , wherein the ceramic filler particles comprise silica particles having a maximum diameter of about 0.6 μm.
6. The semiconductor device assembly of claim 5 , wherein a packing density of the silica particles is between about 0.5 and about 0.95 by volume.
7. The semiconductor device assembly of claim 1 , wherein the second via is tapered from a first diameter to a second diameter.
8. The semiconductor device assembly of claim 7 , wherein the first diameter is between about 10 μm and about 100 μm, and the second diameter is between about 10 μm and about 150 μm.