2D material to integrate 3D horizontal nanosheets using a carrier nanosheet
One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a first carrier nanosheet at least partially surrounded by a first 2D material and a second carrier nanosheet at least partially surrounded by a second 2D material. The transistor can include a first source/drain structure in electrical contact with a first end of the first 2D material and a first end of the second 2D material. The transistor can include a second source/drain structure in electrical contact with a second end of the first 2D material and a second end of the second 2D material. The transistor can include a gate structure at least partially surrounding the first 2D material and the second 2D material.
1. A transistor, comprising:
a first carrier nanosheet;
a first two-dimensional (2D) material surrounding the first carrier nanosheet, and comprising a first portion and a second portion extending along sidewall portions of the first carrier nanosheet, respectively;
a second carrier nanosheet;
a second 2D material surrounding the second carrier nanosheet, and comprising a first portion and a second portion extending along sidewall portions of the second carrier nanosheet, respectively;
a first source/drain structure in electrical contact with the first and second 2D materials through the first portion of the first 2D material and the first portion of the second 2D material, respectively;
a second source/drain structure in electrical contact with the first and second 2D materials through the second portion of the first 2D material and the second portion of the second 2D material, respectively; and
a gate structure at least partially surrounding the first 2D material and the second 2D material,
wherein the first carrier nanosheet laterally extends from the first source/drain structure to the second source/drain structure, with only the first portion of the first 2D material interposed between the first source/drain structure and the first carrier nanosheet and with only the second portion of the first 2D material interposed between the second source/drain structure and the first carrier nanosheet, and wherein the second carrier nanosheet laterally extends from the first source/drain structure to the second source/drain structure, with only the first portion of the second 2D material interposed between the first source/drain structure and the second carrier nanosheet and with only the second portion of the second 2D material interposed between the second source/drain structure and the second carrier nanosheet.
2. The transistor of claim 1 , further comprising a high-k gate material formed between the gate structure and the first 2D material and between the gate structure and the second 2D material.
3. The transistor of claim 1 , further comprising a first dielectric material electrically insulating the gate structure from the first source/drain structure and a second dielectric material electrically insulating the gate structure from the second source/drain structure.
4. The transistor of claim 1 , wherein the first 2D material is disposed between a top surface of the first carrier nanosheet and a first high-k gate material and between a bottom surface of the first carrier nanosheet and the first high-k gate material.
5. The transistor of claim 4 , wherein the second 2D material is disposed between a top surface of the second carrier nanosheet and a second high-k gate material and between a bottom surface of the second carrier nanosheet and the second high-k gate material.
6. The transistor of claim 5 , wherein the gate structure is disposed between the first high-k gate material and the second high-k gate material.
7. The transistor of claim 1 , wherein the gate structure at least partially surrounding the first 2D material is common with the gate structure at least partially surrounding the second 2D material.
8. The transistor of claim 1 , wherein the first 2D material is different from the second 2D material.
9. The transistor of claim 1 , wherein the first and second carrier nanosheets are parallel with one another, the second carrier nanosheet above the first carrier nanosheet and parallel with a substrate.
10. A method comprising:
forming a first carrier nanosheet;
forming a first two-dimensional (2D) material surrounding the first carrier nanosheet, the first 2D material comprising a first portion and a second portion extending along sidewall portions of the first carrier nanosheet, respectively;
forming a second carrier nanosheet;
forming a second 2D material surrounding the second carrier nanosheet, the second 2D material comprising a first portion and a second portion extending along sidewall portions of the second carrier nanosheet, respectively;
forming a first source/drain structure in electrical contact with the first and second 2D materials through the first portion of the first 2D material and the first portion of the second 2D material, respectively;
forming a second source/drain structure in electrical contact with the first and second 2D materials through the second portion of the first 2D material and the second portion of the second 2D material, respectively; and
forming a gate structure at least partially surrounding the first 2D material and the second 2D material,
wherein the first carrier nanosheet laterally extends from the first source/drain structure to the second source/drain structure, with only the first portion of the first 2D material interposed between the first source/drain structure and the first carrier nanosheet and with only the second portion of the first 2D material interposed between the second source/drain structure and the first carrier nanosheet, and wherein the second carrier nanosheet laterally extends from the first source/drain structure to the second source/drain structure, with only the first portion of the second 2D material interposed between the first source/drain structure and the second carrier nanosheet and with only the second portion of the second 2D material interposed between the second source/drain structure and the second carrier nanosheet.
11. The method of claim 10 , further comprising forming a high-k gate material between the gate structure and the first 2D material and between the gate structure and the second 2D material.
12. The method of claim 10 , further comprising forming a first dielectric material electrically insulating the gate structure from the first source/drain structure and a second dielectric material electrically insulating the gate structure from the second source/drain structure.
13. The method of claim 10 , further comprising forming the first 2D material disposed between a top surface of the first carrier nanosheet and a first high-k gate material and between a bottom surface of the first carrier nanosheet and the first high-k gate material.
14. The method of claim 13 , further comprising forming the second 2D material disposed between a top surface of the second carrier nanosheet and a second high-k gate material and between a bottom surface of the second carrier nanosheet and the second high-k gate material.
15. The method of claim 14 , further comprising forming the gate structure disposed between the first high-k gate material and the second high-k gate material.
16. The method of claim 10 , further comprising forming the gate structure at least partially surrounding the first 2D material common with the gate structure at least partially surrounding the second 2D material.
17. The method of claim 10 , further comprising forming the first 2D material different from the second 2D material.
18. The method of claim 10 , further comprising the first and second carrier nanosheets parallel with one another, the second carrier nanosheet above the first carrier nanosheet and parallel with a substrate.
19. A device comprising:
a source contact having a sidewall surface;
a drain contact having a sidewall surface;
a carrier nanosheet;
a two-dimensional (2D) material comprising a plurality of portions, a first one of the plurality of portions extending along a first sidewall of the carrier nanosheet and interposed between the sidewall surface of the source contact and the first sidewall of the carrier nanosheet, and a second one of the plurality of portions extending along a second sidewall of the carrier nanosheet and interposed between the sidewall surface of the drain contact and the second sidewall of the carrier nanosheet; and
a gate structure isolated from the source and drain contacts and provided on at least one side of the 2D material, the gate structure comprising a gate contact and a gate dielectric between the gate contact and the 2D material,
wherein the carrier nanosheet laterally extends from the source contact to the drain contact, with only the first portion of the 2D material interposed between the source contact and the carrier nanosheet and with only the second portion of the 2D material interposed between the drain contact and the carrier nanosheet.
20. The device of claim 19 , wherein the 2D material is supported by the carrier nanosheet, and at least a third one of the plurality of portions of the 2D material is disposed between a top or bottom surface of the carrier nanosheet and the gate dielectric.