IP Library › Granted Patent US 11,635,703
Granted Patent B2
US 11,635,703 · App. 17/584,516 · Granted Apr 25, 2023

Light emitting device and image forming apparatus including light emitting device

Inventors: Yasutomo Furuta (Chiba, JP); Takahisa Ono (Kanagawa, JP); Hayato Koyama (Chiba, JP); Hidefumi Yoshida (Chiba, JP)
Assignee: Canon Kabushiki Kaisha
G03G15/04054G03G15/041B41J2/447B41J2/45G03G2215/0409H01L51/50
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Quick Facts
Patent No.
US 11,635,703
App. No.
17/584,516
Granted
Apr 25, 2023
Kind
B2
Abstract

A light emitting device 401 includes a silicon substrate and a light emitting region including a lower electrode, a light emitting layer, and an upper electrode, and an exposure head is provided with a printed board on which light emitting devices 401 are arranged in a staggered form and a circuit portion 602 for controlling, on the basis of image data, a voltage of each of electrodes included in the lower electrode so that the light emitting device layer emits light and is for forming an image with a resolution corresponding to an arrangement interval of the lower electrode with respect to a crossing direction, and the circuit portion 602 is disposed together with the light emitting region on the silicon substrate. Costs on wire bonding and an area of a wiring board can be suppressed.

Claims (25)

1. An image forming apparatus comprising:

a photosensitive member for being rotationally driven about a rotational axis, the photosensitive member including a photosensitive member surface;

an exposure head including a light emitting device, a circuit board on which the light emitting device is mounted, and a lens array for guiding light emitted from the light emitting device to the photosensitive member surface; and

a controller for outputting image data for driving the light emitting device, to the circuit board,

wherein the light emitting device comprises:

a silicon wafer including a driving circuit for driving the light emitting device; and

a laminar member including a first electrode layer that includes a plurality of electrodes arranged in a direction substantially parallel to the rotational axis of the photosensitive member, a second electrode layer through which light is transmittable and which is laminar, and a light emitting layer formed in a layer between the first electrode layer and the second electrode layer and for emitting light by application of a voltage, the laminar member being formed on a surface of the silicon wafer, and

wherein the driving circuit includes a voltage generating circuit for generating a driving voltage and a pulse signal generating circuit for generating a pulse signal for each of the plurality of electrodes on the basis of the image data, and the driving circuit applies the driving voltage, generated by the voltage generating circuit, to each of the plurality of electrodes depending on the pulse signal.

2. An image forming apparatus according to claim 1 , wherein the first electrode layer is formed separately on the silicon wafer, the light emitting layer is formed in the layer on the first electrode layer, and the second electrode layer is formed on a side opposite from a side where the silicon wafer is disposed while sandwiching the light emitting layer between the second electrode layer and the first electrode layer.

3. An image forming apparatus according to claim 1 , wherein the driving circuit includes a shift register including a plurality of flip-flop circuits which correspond to the plurality of electrodes, respectively, and which are for storing the image data, and the driving circuit includes a register including a plurality of flip-flop circuits which correspond to the plurality of electrodes, respectively, and which are individually connected to the plurality of flip-flop circuits, respectively, of the shift register, and

wherein the pulse signal generating portion generates the pulse signal on the basis of the image data stored in the flip-flop circuits of the register.

4. An image forming apparatus according to claim 3 , wherein the controller generates a clock signal and a line synchronization signal,

wherein the shift register samples the image data outputted by the controller in synchronism with the clock signal and shifts the image data in the plurality of flip-flop circuits thereof, and

wherein the image data stored in the flip-flop circuits, respectively, corresponding to the plurality of electrodes of the shift register are transferred to the flip-flop circuits of the register depending on the line synchronization signal.

5. An image forming apparatus according to claim 1 , wherein a plurality of the light emitting devices are disposed on the circuit board along the direction substantially parallel to the rotational axis.

6. An image forming apparatus according to claim 5 , wherein the controller and the plurality of light emitting devices are connected by a common signal line for transmitting the image data from the controller to the plurality of light emitting devices, and

wherein the controller outputs an enabling signal for enabling sampling of the image data to one light emitting device of the plurality of light emitting devices, and each of the plurality of light emitting devices successively delivers the enabling signal in a delayed manner by using the one light emitting device as a starting point.

7. An image forming apparatus according to claim 5 , wherein the plurality of light emitting devices are divided into a first light emitting device group connected to the controller by a common signal line for transmitting the image data and a second light emitting device group connected to the controller by a common second signal line for transmitting the image data, and

wherein the controller outputs an enabling signal for enabling sampling of the image data to each of one light emitting device of the plurality of light emitting devices included in the first light emitting device group and one light emitting device of the plurality of light emitting devices included in the second light emitting device group, and each of the plurality of light emitting devices included in each of the light emitting device groups successively delivers the enabling signal in a delayed manner by using the one light emitting device of the plurality of light emitting devices included in the first light emitting device group and the one light emitting device of the plurality of light emitting devices included in the second light emitting device group as a starting point.

8. A light emitting device comprising:

a silicon wafer including a circuit; and

a laminar member including a first electrode layer that includes a plurality of electrodes, a second electrode layer through which light is transmittable and which is laminar, and a light emitting layer formed in a layer between the first electrode layer and the second electrode layer and for emitting light by application of a voltage, the laminar member being formed on a surface of the silicon wafer,

wherein the driving circuit includes a voltage generating circuit for generating a driving voltage and a pulse signal generating circuit for generating a pulse signal for each of the plurality of electrodes on the basis of driving data, and the driving circuit applies the driving voltage, generated by the voltage generating circuit, to each of the plurality of electrodes depending on the pulse signal.

9. A light emitting device according to claim 8 , wherein the first electrode layer is formed separately on the silicon wafer, the light emitting layer is formed in the layer on the first electrode layer, and the second electrode layer is formed on a side opposite from a side where the silicon wafer is disposed while sandwiching the light emitting layer between the second electrode layer and the first electrode layer.

10. A light emitting device according to claim 8 , wherein the driving circuit includes a shift register including a plurality of flip-flop circuits which correspond to the plurality of electrodes, respectively, and which are for storing the image data, and the driving circuit includes a register including a plurality of flip-flop circuits which correspond to the plurality of electrodes, respectively, and which are individually connected to the plurality of flip-flop circuits, respectively, of the shift register, and wherein the pulse signal generating portion generates the pulse signal on the basis of the image data stored in the flip-flop circuits of the register.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2022
From: FURUTA, YASUTOMO; ONO, TAKAHISA; KOYAMA, HAYATO; YOSHIDA, HIDEFUMI
To: CANON KABUSHIKI KAISHA
Reel/Frame 059331/0355 →
Priority Claims (3)
JP JP2019-152969 · Aug 23, 2019 · national
JP JP2019-152970 · Aug 23, 2019 · national
JP JP2020-124707 · Jul 21, 2020 · national
Continuity (2)
Continuation PCTJP2020030287 · Jul 31, 2020
Related Publication 20220146959A1 · May 12, 2022
Cited By (1)
US 12,699,336