IP Library Granted Patent US 12,165,809
Granted Patent B2
US 12,165,809 · App. 17/584,543 · Granted Dec 10, 2024

3D capacitor and capacitor array fabricating photoactive substrates

Inventors: Jeb H. Flemming (Albuquerque, NM); Jeff A. Bullington (Orlando, FL); Kyle McWethy (Albuquerque, NM)
Assignee: 3D GLASS SOLUTIONS, INC.
H01G4/008H01G4/012H01G4/08H01G4/129H01G4/33H01G4/38H05K3/0002H01G4/12
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Quick Facts
Patent No.
US 12,165,809
App. No.
17/584,543
Granted
Dec 10, 2024
Kind
B2
Abstract

The present invention provides a method of fabrication and device made by preparing a photosensitive glass substrate comprising at least silica, lithium oxide, aluminum oxide, and cerium oxide, masking a design layout comprising one or more holes or post to form one or more high surface area capacitive device for monolithic system level integration on a glass substrate.

Claims (43)

1. A method of making a capacitive device within one or more three-dimensional structures etched within a single photosensitive glass ceramic substrate, comprising:

providing a photosensitive glass ceramic substrate comprising silica, lithium oxide, aluminum oxide, and cerium oxide;

masking a design layout on the photosensitive glass ceramic substrate, wherein the design layout comprises one or more structures to form one or more three-dimensional structures;

exposing at least one portion of the photosensitive glass ceramic substrate to an activating energy source;

heating the photosensitive glass ceramic substrate for at least ten minutes to a temperature above its glass transition temperature;

cooling the photosensitive glass ceramic substrate to transform at least part of the exposed photosensitive glass ceramic substrate to a crystalline material to form a glass-crystalline substrate;

etching the glass-crystalline substrate with an etchant solution to form the one or more three-dimensional etched structures in the glass-crystalline substrate, wherein the etched glass-crystalline substrate and an unexposed portion of the photosensitive glass substrate have an anisotropic etch ratio of at least 30:1;

rinsing an interior surface of each of the one or more three dimensional etched structures with a dilute glass etchant to increase the surface area of the interior surface to increase a capacitance of the glass ceramic capacitive device;

coating at least a portion of the interior surface of each of the one or more three dimensional etched structures with a first metal to form a bottom electrode;

coating at least a portion of the bottom electrode with a dielectric media;

coating at least a portion of the dielectric media with a second metal to form a top electrode; and

removing at least a portion of the top electrode and the dielectric media to provide an electrical contact configured to make an electrical connection between the capacitive device and a circuitry.

2. The method of claim 1 , further comprising converting a portion of the glass-crystalline substrate adjacent to the one or more three dimensional etched structures to a ceramic phase.

3. The method of claim 1 , wherein the coating with the first metal, the coating with the second metal, or both are performed with atomic layer deposition (ALD).

4. The method of claim 1 , wherein the first metal, the second metal, or both comprise Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, Al 2 O 3 , a mixture of two or more thereof, or an alloy of two or more thereof.

5. The method of claim 1 , wherein the dielectric layer comprises Ta 2 O 5 , Al 2 O 3 or another vapor-phase dielectric, or a combination thereof.

6. A capacitive device comprising:

a photosensitive glass ceramic substrate comprising:

silica, lithium oxide, aluminum oxide, and cerium oxide;

a glass-crystalline substrate; and

one or more three-dimensional structures etched in the glass-crystalline substrate, wherein the glass-crystalline substrate and a non-glass-crystalline portion of the photosensitive glass substrate have an anisotropic etch ratio of at least 30:1, each three-dimensional structure comprising an interior surface with a high-surface-area texture;

a first metal coating disposed on at least a portion the interior surface of each three-dimensional structure as a bottom electrode;

a dielectric coating disposed on a least a portion of the bottom electrode;

a second metal coating disposed on at least a portion of the dielectric coating as a top electrode; and

one or more surface contacts or one or more buried contacts in electrical communication with the bottom electrode or the top electrode and configured to be connected to a circuitry.

7. The device of claim 6 , further comprising a ceramic phase adjacent to the one or more three dimensional etched structures.

8. The device of claim 6 , wherein the coating with the first metal, the coating with the second metal, or both are disposed with atomic layer deposition (ALD).

9. The device of claim 6 , wherein the first metal, the second metal, or both comprise Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, Al 2 O 3 , a mixture of two or more thereof, or an alloy of two or more thereof.

10. The device of claim 6 , wherein the dielectric layer comprises Ta 2 O 5 , Al 2 O 3 , another vapor-phase dielectric, or a combination thereof.

11. A capacitive device comprising:

a single photosensitive glass ceramic substrate comprising:

silica, lithium oxide, aluminum oxide, and cerium oxide;

a first glass-crystalline substrate;

a second glass-crystalline substrate;

a three-dimensional structure etched in the first glass-crystalline substrate and the second glass-crystalline substrate, wherein the first and second glass-crystalline substrates and a non-glass-crystalline portion of the photosensitive glass substrate have an anisotropic etch ratio of at least 30:1;

a first metal coating disposed on the first glass-crystalline substrate;

a second metal coating disposed on the second glass-crystalline substrate;

a layer of dielectric material disposed between the first glass-crystalline substrate and the second glass-crystalline substrate; and

one or more vias, one or more post channels, or a combination thereof directly connecting the first glass-crystalline substrate and the second glass-crystalline substrate, wherein the one or more vias or one or more post channels are formed having a high-surface area texture that provides an increased capacitance in the capacitive device.

12. The device of claim 11 , further comprising a ceramic phase adjacent to the three-dimensional structure.

13. The device of claim 11 , wherein the first metal coating, the second metal coating, or both are disposed with atomic layer deposition (ALD).

14. The device of claim 11 , wherein the first metal, the second metal, or both comprise Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, Al 2 O 3 , a mixture of two or more thereof, or an alloy of two or more thereof.

15. The device of claim 11 , wherein the dielectric material comprises Ta 2 O 5 , Al 2 O 3 , another vapor-phase dielectric, or a combination thereof.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2022
From: FLEMMING, JEB H.; BULLINGTON, JEFF; MCWETHY, KYLE
To: 3D GLASS SOLUTIONS, INC.
Reel/Frame 058925/0551 →
Continuity (3)
Continuation In Part 16079033
Provisional Application 62299641 · Feb 25, 2016
Related Publication 20220157524A1 · May 19, 2022