eFUSE one-time programmable memory with inter integrated circuit (I2C) communication and operation method thereof

1. An eFuse one-time programmable (OTP) memory, comprising:

an eFuse configured to perform one-time writing and multiple readings for a plurality of addresses;

an inter integrated circuit (I2C) slave, configured to communicate with an I2C master via a serial clock line and a serial data line, and perform data writing and data reading to and from the eFuse, wherein the I2C slave includes:

an I2C slave interface, configured to communicate with the I2C master,

a register block, configured to store serial data received from the I2C master through the serial data line, and store data read from the eFuse IP,

an efuse controller, configured generate a control signal to write data to the eFuse IP or to read data stored in the eFuse IP, based on the serial received through the serial data line, and

a clock control, configured to provide a clock signal to control operations of the efuse controller;

a serial data input pin which is connected to the serial data line through an open drain input/output device, and is configured to receive the serial data from the I2C master;

a serial data output pin which is connected to the serial data line through the open drain input/output device, and is configured to output data to the I2C master; and

a serial data output enable pin which is configured to output a signal controlling the open drain input/output such that the serial data input pin or the serial data output pin is connected to the serial data line.

2. The eFuse OTP memory of claim 1 ,

wherein the I2C slave is configured to:

receive a data write condition through the serial data line in a first cycle,

receive first data to be programmed in the eFuse through the serial data line in a second cycle,

receive an address of the eFuse to program the first data through the serial data line in a third cycle, and

write the first data to the address of the eFuse, based on the received data write condition.

3. The eFuse OTP memory of claim 2 , wherein the data write condition comprises at least one of a fusing current value to be used while writing the first data to the address of the eFuse, whether to select a read mode, or whether to check a margin of a resistance value of an initial eFuse.

4. The eFuse OTP memory of claim 2 ,

wherein the I2C slave is further configured to:

receive a chip address, an R/W bit, a command register address, and the data write condition through the serial data line in the first cycle, and store the data write condition in the command register address of the register block,

receive the chip address, the R/W bit, a data register address, and the first data to be programmed in the eFuse through the serial data line in the second cycle, and store the first data in the data register address of the register block,

receive the chip address, the R/W bit, an address register address, and the address of the eFuse through the serial data line in the third cycle, and store the address of the eFuse in the address register address of the register block, and

transmit a first ack signal through the serial data line, every predetermined period in each cycle, and

wherein the R/W bit is set such that a write operation is performed in the first cycle, the second cycle, and the third cycle.

5. The eFuse OTP memory of claim 1 ,

wherein the I2C slave is configured to:

receive a data read condition through the serial data line in a first cycle,

receive an address of the eFuse through the serial data line in a second cycle, and

transmit second data read from the eFuse based on the address of the eFuse to the I2C master through the serial data line in a third cycle.

6. The eFuse OTP memory of claim 5 , wherein the data read condition comprises at least one of whether to select a read mode, or whether to check a margin of a resistance value of an initial eFuse.

7. The eFuse OTP memory of claim 5 ,

wherein the I2C slave is further configured to:

receive a chip address, an R/W bit, a command register address, and the data read condition through the serial data line in the first cycle, and store the data read condition in the command register address of the register block,

receive the chip address, the R/W bit, and the address of the eFuse through the serial data line in the second cycle,

receive the chip address and the R/W bit through the serial data line in the third cycle, and transmit, through the serial data line, the second data read from the eFuse based on the address of the eFuse to the I2C master, and

transmit a first ack signal through the serial data line, every predetermined period in each cycle.

8. The eFuse OTP memory of claim 7 , wherein the R/W bit indicates which of a write operation and a read operation is performed in a corresponding cycle, and is set to indicate that the write operation is performed in the first cycle and in the second cycle and to indicate that the read operation is performed in the third cycle.

9. The eFuse OTP memory of claim 7 , wherein the I2C slave is further configured to transmit, through the serial data line in the third cycle, the second data read from the eFuse based on the address of the eFuse to the I2C master, and receive a second ack signal indicating that the read operation is completed.