Semiconductor dies including low and high workfunction semiconductor devices

1. A semiconductor die, comprising:

a first set of semiconductor devices disposed at a first location of the semiconductor die, each of the first set of semiconductor devices having a first workfunction to cause each of the first set of semiconductor devices to store memory for a first time period; and

a second set of semiconductor devices disposed at a second location of the semiconductor die different from the first location, each of second set of semiconductor devices having a second workfunction that is greater than the first workfunction to cause each of the second set of semiconductor devices to store memory for a second time period greater than the first time period, wherein each of the first and the second set of semiconductor devices comprises:

a source;

a drain spaced apart from the source in a first direction by an inner spacer; and

a channel layer disposed radially outwards of radially outer surfaces of the inner spacer, the source and the drain in a second direction perpendicular to the first direction and extending in the first direction.

2. The semiconductor die of claim 1 , wherein, each of the first and second set of semiconductor devices further comprises:

a memory layer disposed on a radially outer surface of the channel layer in the second direction and extending in the first direction; and

at least one gate layer disposed on a radially outer surface of the memory layer in the second direction and extending in the first direction.

3. The semiconductor die of claim 2 , wherein:

the at least one gate layer included in each of the first set of semiconductor devices comprises a first material to cause the each of the first set of semiconductor devices to have the first workfunction; and

the at least one gate layer included in each of the second set of semiconductor devices comprises a second material different from the first material to cause each of the second set of semiconductor devices to have the second workfunction.

4. The semiconductor die of claim 2 , wherein:

each of the at least one gate layer included in the first set of semiconductor devices comprises a n-type material; and

the second set of semiconductor devices further comprises a barrier layer interposed between the memory layer and the at least one gate layer included in each of the second set of semiconductor devices.

5. The semiconductor die of claim 4 , wherein a first thickness of the at least one gate layer included in each of the first set of semiconductor devices is approximately equal to a sum of a second thickness of the at least one gate layer included in each of the second set of semiconductor devices and a thickness of the barrier layer included in each of the second set of semiconductor devices.

6. The semiconductor die of claim 2 , wherein:

each of the at least one gate layer included in the first set and the second set of semiconductor devices comprises a n-type material;

each of the first set of semiconductor devices comprises a first barrier layer interposed between the memory layer and the at least one gate layer included in each of the first set of semiconductor devices, the first barrier layer having a first barrier thickness; and

each of the second set of semiconductor devices comprises a second barrier layer interposed between the memory layer and the at least one gate layer included in each of the second set of semiconductor devices, the second barrier layer having a second barrier thickness greater than the first barrier thickness.

7. The semiconductor die of claim 2 , wherein:

each of the at least one gate layer included in the first set and the second set of semiconductor devices comprises a p-type material;

each of the first set of semiconductor devices comprise a first barrier layer interposed between the memory layer and the at least one gate layer included in each of the first set of semiconductor devices, the first barrier layer having a first barrier thickness; and

each of the second set of semiconductor devices comprise a second barrier layer interposed between the memory layer and the at least one gate layer included in each of the second set of semiconductor devices, the second barrier layer having a second barrier thickness that is less than the first barrier thickness.

8. The semiconductor die of claim 7 , wherein:

a first sum of a thickness of the at least one gate layer included in each of the first set of semiconductor devices and the first barrier thickness is approximately equal to a second sum of a thickness of the at least one gate layer included in each of the second set of semiconductor devices and the second barrier thickness.

9. The semiconductor die of claim 2 , wherein:

a first channel thickness of the channel layer included in each of the first set of semiconductor devices is different from a second channel thickness of the channel layer included in each of the second set of semiconductor devices.

10. The semiconductor die of claim 2 , wherein:

a first channel material of the channel layer included in each of the first set of semiconductor devices is different from a second channel material of the channel layer included in each of the second set of semiconductor devices.

11. The semiconductor die of claim 10 , wherein the at least one gate layer included in each of the first set of semiconductor devices comprises a first material that is different from a second material of the at least one gate layer included in each of the second set of semiconductor devices.

12. The semiconductor die of claim 1 , wherein:

the first location is a first side of the semiconductor die in a first direction, a first array of the first set of semiconductor devices is disposed on the first side;

the second location is a second side of the semiconductor die in the first direction opposite the first side, a second array of the second set of semiconductor devices being disposed on the second side; and

an array isolation layer is interposed between the first array and the second array.

13. The semiconductor die of claim 1 , wherein:

the first set of semiconductor devices is disposed adjacent to the second set of semiconductor devices in at least a first direction, a second direction perpendicular to the first direction, or the first direction and the second direction; and

an array isolation layer is interposed between the first set and the second set of semiconductor devices.

14. A semiconductor die, comprising:

a first set of semiconductor devices disposed at a first location of the semiconductor die, and a second set of semiconductor devices disposed at a second location of the semiconductor die different from the first location, each of the first and second set of semiconductor devices comprising:

a source,

a drain spaced apart from the source in a first direction by an inner spacer;

a channel layer disposed radially outwards of radially outer surfaces of the inner spacer, the source and the drain in a second direction perpendicular to the first direction and extending in the first direction;

a memory layer disposed on a radially outer surface of the channel layer in the second direction and extending in the first direction; and

at least one first gate layer disposed on a radially outer surface of the memory layer,

wherein the at least one gate layer included in each of the first set of semiconductor devices has a first property and the at least one gate layer included in each of the second set of semiconductor devices has a second property different from the first property, the first property configured to cause each of the first set of semiconductor devices to have a first workfunction, and the second property configured to cause each of the second set of semiconductor devices to have a second workfunction greater than the first workfunction.

15. The semiconductor die of claim 14 , wherein:

the at least one gate layer included in each of the first set of semiconductor devices comprises a first material; and

the at least one gate layer included in each of the second set of semiconductor devices comprises a second material different from the first material.

16. The semiconductor die of claim 14 , wherein:

each of the at least one gate layer included in the first set of semiconductor devices comprises a n-type material;

the second set of semiconductor devices further comprises a barrier layer interposed between the memory layer and the at least one gate layer included in each of the second set of semiconductor devices; and

a first thickness of the at least one gate layer included in each of the first set of semiconductor devices is approximately equal to a sum of a second thickness of the at least one gate layer included in each of the second set of semiconductor devices and a thickness of the barrier layer included in each of the second set of semiconductor devices.

17. The semiconductor die of claim 14 , wherein:

each of the at least one gate layers included in the first set and the second set of semiconductor devices comprises a n-type material;

each of the first set of semiconductor devices comprises a first barrier layer interposed between the memory layer and the at least one gate layer included in each of the first set of semiconductor devices, the first barrier layer having a first barrier thickness; and

each of the second set of semiconductor devices comprises a second barrier layer interposed between the memory layer and the at least one gate layer included in each of the second set of semiconductor devices, the second barrier layer having a second barrier thickness greater than the first barrier thickness.

18. The semiconductor die of claim 14 , wherein:

each of the at least one gate layer included in the first set and the second set of semiconductor devices comprises a p-type material;

each of the first set of semiconductor devices comprises a first barrier layer interposed between the memory layer and the at least one gate layer included in each of the first set of semiconductor devices, the first barrier layer having a first barrier thickness;

each of the second set of semiconductor devices comprise a second barrier layer interposed between the memory layer and the at least one gate layer included in each of the second set of semiconductor devices, the second barrier layer having a second barrier thickness that is less than the first barrier thickness; and

a first sum of a thickness the at least one gate layer included in each of the first set of semiconductor devices and the first barrier thickness is approximately equal to a second sum of a thickness of the at least one gate layer included in each of the second set of semiconductor devices and the second barrier thickness.

19. A semiconductor die, comprising:

a first set of semiconductor devices disposed at a first location of the semiconductor die; and

a second set of semiconductor devices disposed at a second location of the semiconductor die different from the first location;

wherein each of the first and the second set of semiconductor devices comprises:

a source;

a drain spaced apart from the source in a first direction by an inner spacer;

a channel layer disposed radially outwards of radially outer surfaces of the inner spacer, the source and the drain in a second direction perpendicular to the first direction and extending in the first direction; and

a memory layer disposed on a radially outer surface of the channel layer in the second direction and extending in the first direction.

20. The semiconductor die of claim 19 , wherein each of the first set of semiconductor devices has a first workfunction to cause each of the first set of semiconductor devices to store memory for a first time period, and wherein each of the second set of semiconductor devices has a second workfunction greater than the first workfunction to cause each of the second set of semiconductor devices to store memory for a second time period greater than the first time period.