Hardware acceleration for function processing

1. A computer-implemented method, comprising:

determining that a hardware acceleration condition has been satisfied for a first function by:

counting, within a time interval, a number of requests or instructions received by a function processing service to perform the first function; and

determining that the number of requests or instructions to perform the first function exceeds a threshold value;

configuring a hardware circuit to perform the first function;

adding the first function to a function library that is implemented in the hardware circuit;

receiving, at the function processing service, a request to execute source code, wherein the source code comprises the instructions to perform the first function; and

causing the first function to be performed via the hardware circuit.

2. The computer-implemented method of claim 1 , wherein:

the hardware circuit comprises a field programmable gate array (FPGA); and

the computer-implemented method further comprises translating the source code into hardware description language (HDL) code corresponding to the FPGA.

3. The computer-implemented method of claim 1 , wherein:

the hardware circuit comprises a graphics processing unit (GPU); and

the computer-implemented method further comprises translating the source code into GPU code.

4. The computer-implemented method of claim 1 , wherein:

the hardware circuit comprises a programmable application-specific integrated circuit (ASIC); and

the computer-implemented method further comprises using a custom compiler to translate the source code into machine code corresponding to the programmable ASIC.

5. The computer-implemented method of claim 1 , wherein:

the hardware circuit comprises a digital signal processor (DSP); and

the computer-implemented method further comprises translating the source code into DSP code.

6. The computer-implemented method of claim 1 , wherein determining that the hardware acceleration condition has been satisfied comprises:

counting the number of requests to perform the first function that the function processing service receives within the time interval; and

determining that the number of requests exceeds the threshold value.

7. The computer-implemented method of claim 1 , wherein the first function belongs to a family of functions, and wherein determining that the hardware acceleration condition has been satisfied further comprises:

counting a combined number of requests to perform any function within the family of functions that the function processing service receives within a time interval including the number of requests to perform the first function; and

determining that the combined number of requests exceeds the threshold value.

8. The computer-implemented method of claim 1 , wherein determining that the hardware acceleration condition has been satisfied further comprises:

determining an estimated cost savings associated with performing the number of instructions of the first function via the hardware circuit compared to performing the first function via a general-purpose processor; and

determining that the estimated cost savings exceed the threshold value.

9. The computer-implemented method of claim 1 , further comprising configuring the hardware circuit to perform a second function in parallel with the first function, wherein the second function is different from the first function.

10. The computer-implemented method of claim 9 , further comprising configuring the hardware circuit to operate a plurality of instances of the hardware circuit in parallel.

11. A system, comprising:

at least one processor;

memory in electronic communication with the at least one processor; and

instructions stored in the memory, the instructions being executable by the at least one processor to perform operations of:

determining that a hardware acceleration condition has been satisfied for a first function by:

counting, within a time interval, a number of requests or instructions received by a function processing service to perform the first function; and

determining that the number of requests or instructions to perform the first function exceeds a threshold value;

configuring a hardware circuit to perform the first function;

adding the first function to a function library that is implemented in the hardware circuit;

receiving, at the function processing service, a request to execute source code, wherein the source code comprises the instructions to perform the first function; and

causing the first function to be performed via the hardware circuit.

12. The system of claim 11 , wherein:

the hardware circuit comprises a field programmable gate array (FPGA); and

the system further comprises translating the source code into hardware description language (HDL) code corresponding to the FPGA.

13. The system of claim 11 , wherein:

the hardware circuit comprises a graphics processing unit (GPU); and

the system further comprises translating the source code into GPU code.

14. The system of claim 11 , wherein:

the hardware circuit comprises a programmable application-specific integrated circuit (ASIC); and

the system further comprises using a custom compiler to translate the source code into machine code corresponding to the programmable ASIC.

15. The system of claim 11 , wherein:

the hardware circuit comprises a digital signal processor (DSP); and

the system further comprises translating the source code into DSP code.

16. The system of claim 11 , wherein determining that the hardware acceleration condition has been satisfied comprises:

counting the number of requests to perform the first function that the function processing service receives within the time interval; and

determining that the number of requests exceeds the threshold value.

17. The system of claim 11 , wherein the first function belongs to a family of functions, and wherein determining that the hardware acceleration condition has been satisfied further comprises:

counting a combined number of requests to perform any function within the family of functions that the function processing service receives within a time interval including the number of requests to perform the first function; and

determining that the combined number of requests exceeds the threshold value.

18. The system of claim 11 , further comprising instructions being executable by the at least one processor to configure the hardware circuit to perform a second function in parallel with the first function, wherein the second function is different from the first function.

19. A non-transitory computer-readable medium storing instructions thereon that, when executed by at least one processor, causes a computing device to:

determine that a hardware acceleration condition has been satisfied for a first function by:

counting, within a time interval, a number of requests or instructions received by a function processing service to perform the first function; and

determining that the number of requests or instructions to perform the first function exceeds a threshold value;

add the first function to a function library that is implemented in hardware circuits;

receive, at a function processing service, a request to execute source code, wherein the source code comprises the instructions to perform the first function; and

cause the first function to be performed via the hardware circuits.

20. The non-transitory computer-readable medium of claim 19 , wherein the hardware circuits include one or more of a field programmable gate array (FPGA), a graphics processing unit (GPU), a programmable application specific integrated circuit (ASIC); or a digital signal processor (DSP).