Method for a reliability, availability, and serviceability-conscious huge page support

1. A method, comprising:

in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, wherein the faulted segment is smaller than a memory page; and

in response to receiving from a processor a memory access request directed to the faulted segment, performing the requested memory access at the patch segment based on a patch segment address identifying a location of the patch segment, wherein the patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.

2. The method of claim 1 , further comprising:

in a first memory device, reserving memory capacity as a patch memory region for backing faulted memory, wherein the first memory device comprises a static random access memory (SRAM) device in a local memory controller of a second memory device containing the faulted segment;

storing the remapping table in the first memory device; and

querying the remapping table to determine the patch segment address corresponding to the requested memory address.

3. The method of claim 1 , wherein:

the faulted segment resides in a first memory node of a non-uniform memory access (NUMA) computing system and the patch memory region resides in a second memory node of the NUMA computing system; and

the method further comprises storing the remapping table in a processing node of the NUMA computing system.

4. The method of claim 1 , further comprising:

in response to detecting that one or more threads associated with the faulted segment are executing within the same non-uniform memory access (NUMA) node as the faulted segment, storing the patch memory region in a local memory device residing within the same NUMA node as the faulted segment.

5. The method of claim 1 , further comprising:

in response to determining that a memory device containing the faulted segment is subject to memory wear-out, storing the patch memory region in a dynamic random access (DRAM) memory device in a different NUMA node than the memory device.

6. The method of claim 2 , further comprising:

in a set of reliability, availability, and serviceability (RAS) counters, tracking a rate of uncorrectable errors occurring in a memory device containing the faulted segment; and

determining a size of the memory capacity reserved as the patch memory region based on the rate of uncorrectable errors.

7. The method of claim 1 , further comprising:

prior to receiving the memory access request, copying data from the faulted segment to the patch segment; and

recording an indication that data in a cache line corresponding to the faulted segment is corrupt.

8. The method of claim 1 , further comprising:

in the remapping table, associating a failing segment in a memory device with a second patch segment in the patch memory region in response to an indication that a rate of correctable errors in the failing segment has exceeded a threshold error rate.

9. The method of claim 1 , further comprising:

copying the remapping table to a non-volatile memory; and

restoring the remapping table from the non-volatile memory.

10. A computing device, comprising:

a remapping table; and

control logic circuitry coupled with the remapping table and configured to:

in response to a memory error indication indicating an uncorrectable error in a faulted segment, associate in the remapping table the faulted segment with a patch segment, wherein the faulted segment is smaller than a memory page; and

in response to receiving from a processor a memory access request directed to the faulted segment, performing the requested memory access at the patch segment based on a patch segment address identifying a location of the patch segment, wherein the patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.

11. The computing device of claim 10 , wherein

the control logic circuitry is further configured to:

reserve memory capacity in a first memory device as a patch memory region for backing faulted memory; and

query the remapping table to determine the patch segment address corresponding to the requested memory address,

wherein the first memory device comprises a static random access memory (SRAM) device in a local memory controller of a second memory device containing the faulted segment, and

the first memory device is configured to store the remapping table.

12. The computing device of claim 11 , further comprising:

a set of reliability, availability, and serviceability (RAS) counters configured to track a rate of uncorrectable errors occurring in a memory device containing the faulted segment, wherein a size of the memory capacity reserved as the patch memory region is determined based on the rate of uncorrectable errors.

13. The computing device of claim 11 , wherein the control logic circuitry is further configured to: in response to detecting that one or more threads associated with the faulted segment are executing within the same non-uniform memory access (NUMA 31 node as the faulted segment, store the patch memory region in a local memory device residing within the same NUMA node as the faulted segment.

14. The computing device of claim 11 , wherein the control logic circuitry is further configured to: in response to determining that a memory device containing the faulted segment is subject to memory wear-out, storing the patch memory region in a dynamic random access (DRAM) memory device in a different NUMA node than the memory device.

15. The computing device of claim 11 , wherein

the control logic circuitry is further configured to: in the remapping table, associate a failing segment in a memory device with a second patch segment in the patch memory region in response to an indication that a rate of correctable errors in the failing segment has exceeded a threshold error rate.

16. A computing system, comprising:

a remapping table;

a memory device configured to store application data; and

control logic coupled with the memory device and configured to:

in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in the remapping table the faulted segment with a patch segment in a patch memory region, wherein the faulted segment is smaller than a memory page; and

in response to receiving from a processor a memory access request directed to the faulted segment, performing the requested memory access at the patch segment based on a patch segment address identifying a location of the patch segment, wherein the patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.

17. The computing system of claim 16 , wherein:

the computing system comprises a plurality of NUMA nodes connected by a data fabric;

the patch memory region and remapping table reside in a first NUMA node;

the memory device resides in a second NUMA node; and

the control logic resides in a processing unit of a processing node.

18. The computing system of claim 16 , wherein:

the control logic is further configured to store the remapping table in a static random access memory (SRAM) device in a local memory controller of the memory device.

19. The computing system of claim 16 , further comprising:

a set of reliability, availability, and serviceability (RAS) counters configured to track a rate of uncorrectable errors occurring in the memory device,

wherein the control logic is further configured to determine a size of memory capacity reserved as the patch memory region based on the rate of uncorrectable errors.

20. The computing system of claim 16 , wherein:

the control logic is further configured to, in the remapping table, associate a failing segment in the memory device with a second patch segment in the patch memory region in response to an indication that a rate of correctable errors in the failing segment has exceeded a threshold error rate.