Photoelectric conversion device and electronic device with a ΔΣ A/D converter

1. A photoelectric conversion device comprising a pixel unit in which a plurality of pixels each including a photoelectric conversion element are arranged in a matrix, and a signal processor configured to process a pixel signal output from the pixel unit via a vertical signal line,

wherein the signal processor comprises a ΔΣ A/D converter configured to convert the pixel signal into a digital signal,

the ΔΣ A/D converter comprises a subtracter which includes a first input terminal to which the pixel signal is input and a second input terminal to which a subtraction signal is input, an integrator configured to receive an output from the subtracter, a comparator configured to compare an output from the integrator with a predetermined voltage, a decimation filter configured to generate the digital signal based on a comparison result output from the comparator, a delay unit configured to delay an output from the comparator, a buffer unit configured to buffer an output from the delay unit, and a D/A converter configured to convert an output from the buffer unit into an analog signal to generate the subtraction signal.

2. The device according to claim 1 , wherein the signal processor further comprises a conversion circuit configured to convert the pixel signal from a voltage signal into a current signal, and

the pixel signal converted into the current signal is input to the subtracter.

3. A photoelectric conversion device comprising a pixel unit in which a plurality of pixels each including a photoelectric conversion element are arranged in a matrix, and a signal processor configured to process a pixel signal output from the pixel unit via a vertical signal line,

wherein the signal processor comprises a conversion circuit configured to convert the pixel signal from a voltage signal into a current signal and a ΔΣ A/D converter configured to convert the pixel signal, which has been converted into the current signal by the conversion circuit, into a digital signal,

the ΔΣ A/D converter includes a subtracter which comprises a first input terminal to which the pixel signal is input and a second input terminal to which a subtraction signal is input, an integrator configured to receive an output from the subtracter, a comparator configured to compare an output from the integrator with a predetermined voltage, a decimation filter configured to generate the digital signal based on a comparison result output from the comparator, a buffer unit configured to buffer an output from the comparator, and a D/A converter configured to convert an output from the buffer unit into an analog signal to generate the subtraction signal.

4. The device according to claim 2 , wherein the integrator comprises a capacitive element which is connected in parallel to the D/A converter.

5. The device according to claim 2 , wherein the D/A converter comprises a current supply source.

6. The device according to claim 2 , wherein the buffer unit is configured to buffer the comparison result to generate a non-inverting signal and an inverting signal based on the comparison result, and

the D/A converter comprises an analog switch configured to operate in accordance with the non-inverting signal and the inverting signal.

7. The device according to claim 1 , wherein the buffer unit comprises an amplifier.

8. The device according to claim 1 , wherein the buffer unit comprises a phase adjuster.

9. The device according to claim 1 , wherein the buffer unit comprises a level shifter.

10. The device according to claim 1 , wherein the subtracter is a first subtracter, the integrator is a first integrator, the D/A converter is a first D/A converter, and the subtraction signal is a first subtraction signal, and

the ΔΣ A/D converter further comprises a second integrator connected between the first integrator and the comparator, a second subtracter which is configured to output a subtraction result to the second integrator and comprises a third input terminal configured to receive an output from the first integrator and a fourth input terminal to which a second subtraction signal is input, and a second D/A converter configured to convert the output from the buffer unit into an analog signal to generate the second subtraction signal.

11. The device according to claim 10 , wherein the buffer unit is configured to buffer the comparison result to perform phase adjustment on the comparison, and is configured to supply comparison results which have different phases from each other to the first D/A converter and the second D/A converter.

12. The device according to claim 11 , wherein the buffer unit is configured to perform phase adjustment so that the phase of the comparison result to be supplied to the first D/A converter will occur ahead of the phase of the comparison result to be supplied to the second D/A converter.

13. The device according to claim 10 , wherein the second integrator comprises a conversion unit configured to convert an output from the second subtracter from a voltage signal into a current signal and a capacitive element which is connected in parallel to the second D/A converter.

14. The device according to claim 13 , wherein the second D/A converter comprises a current supply source.

15. An electronic device comprising:

the photoelectric conversion device according to claim 1 ; and

a control device configured to control an operation of the photoelectric conversion device.