Ferroelectric memory device and operation method thereof
A ferroelectric memory device comprising a plurality of ferroelectric memory elements. Each of the plurality of ferroelectric memory elements includes a channel layer containing a metal oxide, a ferroelectric layer in contact with the channel layer in which the ferroelectric layer contains hafnium oxide, a first gate electrode facing the channel layer via the ferroelectric layer, an insulating layer facing the ferroelectric layer via the channel layer; and a second gate electrode facing the channel layer via the insulating layer.
1. A ferroelectric memory device comprising:
a plurality of ferroelectric memory elements, each of the plurality of ferroelectric memory elements comprising:
a channel layer containing a metal oxide;
a ferroelectric layer in contact with the channel layer, the ferroelectric layer containing hafnium oxide;
a first gate electrode facing the channel layer via the ferroelectric layer;
an insulating layer facing the ferroelectric layer via the channel layer; and
a second gate electrode facing the channel layer via the insulating layer,
wherein a body potential of the channel layer is fixed at a constant potential by the second gate electrode.
2. The ferroelectric memory device according to claim 1 , wherein the insulating layer includes silicon oxide.
3. A ferroelectric memory device comprising:
a plurality of ferroelectric memory elements, each of the plurality of ferroelectric memory elements comprising:
a channel layer containing a metal oxide;
a ferroelectric layer in contact with the channel layer, the ferroelectric layer containing hafnium oxide;
a first gate electrode facing the channel layer via the ferroelectric layer;
an insulating layer facing the ferroelectric layer via the channel layer; and
a second gate electrode facing the channel layer via the insulating layer,
wherein a channel length of the channel layer is 1 μm or less.
4. The ferroelectric memory device according to claim 3 , wherein the channel length of the channel layer is 20 nm or more and 1 μm or less.
5. A ferroelectric memory device comprising:
a plurality of ferroelectric memory elements, each of the plurality of ferroelectric memory elements comprising:
a channel layer containing a metal oxide;
a ferroelectric layer in contact with the channel layer, the ferroelectric layer containing hafnium oxide;
a first gate electrode facing the channel layer via the ferroelectric layer;
an insulating layer facing the ferroelectric layer via the channel layer; and
a second gate electrode facing the channel layer via the insulating layer,
wherein a ratio of a thickness of the insulating layer to a thickness of the channel layer is 1.0 or more and 1.8 or less.
6. A ferroelectric memory device comprising:
a plurality of ferroelectric memory elements, each of the plurality of ferroelectric memory elements comprising:
a channel layer containing a metal oxide;
a ferroelectric layer in contact with the channel layer, the ferroelectric layer containing hafnium oxide; and
a gate electrode facing the channel layer via the ferroelectric layer, wherein
a channel length of the channel layer is 1 μm or less.
7. The ferroelectric memory device according to claim 6 , wherein the channel length of the channel layer is 50 nm or less.
8. The ferroelectric memory device according to claim 7 , wherein the channel length of the channel layer is 20 nm or more and 50 nm or less.
9. The ferroelectric memory device according to claim 6 , wherein the metal oxide is IGZO, ITO, IZO, or ITZO.
10. The ferroelectric memory device according to claim 6 , wherein a thickness of the channel layer is less than 10 nm.
11. The ferroelectric memory device according to claim 10 , wherein the thickness of the channel layer is 1 nm or more and 8 nm or less.
12. The ferroelectric memory device according to claim 6 , wherein a thickness of the ferroelectric layer is 5 nm or more and 20 nm or less.
13. The ferroelectric memory device according to claim 6 , wherein the channel length of the channel layer is 20 nm or more and 1 μm or less.
14. A method of operating a ferroelectric memory device including a plurality of ferroelectric memory elements, each of the plurality of ferroelectric memory elements comprising:
a channel layer containing a metal oxide and having a channel length of 1 μm or less;
a ferroelectric layer in contact with the channel layer, the ferroelectric layer containing hafnium oxide;
a gate electrode facing the channel layer via the ferroelectric layer,
a source electrode in contact with the channel layer, and
a drain electrode separated from the source electrode and in contact with the channel layer,
the method comprising:
an erase operation in which a negative gate voltage is applied to the gate electrodes and a positive first drain voltage is applied to the drain electrodes in at least a part of the plurality of ferroelectric memory elements; and
a program operation in which a positive gate voltage is applied to the gate electrodes and a second drain voltage is applied to the drain electrodes in at least a part of the plurality of ferroelectric memory elements.
15. The method of operating a ferroelectric memory device according to claim 14 , wherein the second drain voltage is a positive voltage or 0V.
16. The method of operating a ferroelectric memory device according to claim 14 , wherein the first drain voltage is greater than the second drain voltage.
17. The method of operating a ferroelectric memory device according to claim 14 , wherein the channel length of the channel layer is 20 nm or more and 1 μm or less.