IP Library › Granted Patent US 12,507,258
Granted Patent B2
US 12,507,258 · App. 17/593,833 · Granted Dec 23, 2025

Range extension for Sidelink Control Information (SCI) stage 2

Inventors: Chunxuan Ye (San Diego, CA); Yushu Zhang (Beijing, CN); Dawei Zhang (Saratoga, CA); Haijing Hu (Los Gatos, CA); Haitong Sun (Cupertino, CA); Wei Zeng (Saratoga, CA); Zhibin Wu (Los Altos, CA)
Assignee: Apple Inc.
H04W72/25H03M13/09H03M13/13H03M13/2906H03M13/635H04L1/0041H04L1/0057H04L1/0061H04L1/0076H04L1/08H04L1/1864H04L5/0053
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Quick Facts
Patent No.
US 12,507,258
App. No.
17/593,833
Granted
Dec 23, 2025
Kind
B2
Abstract

In 5G/New Radio (NR), sidelink communication refers to a channel for communications directly between devices, e.g., user equipment (UEs), without use of traditional uplink or downlink communication channels. Sidelink Control Information (SCI) is separated into two stages (i.e., SCI stage 1 and SCI stage 2) before being transmitted to configure a user device. A method for configuring sidelink communications for a wireless device includes: obtaining SCI Stage 2 payload information; attaching and distributing cyclic redundancy check (CRC) information to the payload information; performing encoding and rate matching (RM) on the payload information; scrambling the encoded and rate matched payload information; performing modulation on the scrambled payload information; determining a resource mapping for the modulated payload information, wherein the modulated payload information is aggregated across two or more slots (e.g., using different processing operations for at least two slots); and transmitting the modulated payload information according to the determined resource mapping.

Claims (45)

1 . A method for configuring communications for a wireless device, comprising:

obtaining sidelink control information (SCI) Stage 2 payload information;

determining a resource mapping for the SCI Stage 2 payload information to a Physical Sidelink Shared Channel (PSSCH), wherein the SCI Stage 2 payload information is aggregated across two or more slots of the PSSCH, and wherein a number of resource elements (REs) used for the SCI Stage 2 payload information in a single slot is proportional to a PSSCH slot aggregation level used and a number of RE changes over successive slots for a transmission of the SCI Stage 2 payload information;

transmitting SCI Stage 1 information on a Physical Sidelink Control Channel (PSCCH), wherein the SCI Stage 1 information indicates the resource mapping for the SCI Stage 2 payload information to the PSSCH;

performing encoding and rate matching on the SCI Stage 2 payload information, wherein the rate matching comprises at least one shortening operation on the SCI Stage 2 payload information in a first slot of the two or more slots of the PSSCH and at least one puncturing operation on the SCI Stage 2 payload information in a second slot of the two or more slots of the PSSCH; and

transmitting the SCI stage 2 payload information on the PSSCH to one or more wireless devices, after performing the encoding, the rate matching, and the determining the resource mapping.

2 . The method of claim 1 , further comprising:

attaching and distributing cyclic redundancy check (CRC) information to the payload information;

scrambling the encoded and rate matched payload information; and

performing modulation on the scrambled payload information.

3 . The method of claim 2 , wherein the encoding comprises a polar encoding operation.

4 . The method of claim 3 , wherein a same polar encoded and rate matched bits are transmitted in each of the aggregated two or more slots.

5 . The method of claim 3 , wherein different polar encoded and rate matched bits are transmitted over at least two of the aggregated two or more slots.

6 . A wireless device, comprising:

a radio; and

a processor operably coupled to the radio,

wherein the wireless device is configured to:

obtain sidelink control information (SCI) Stage 2 payload information;

determine a resource mapping for the SCI Stage 2 payload information to a Physical Sidelink Shared Channel (PSSCH), wherein the SCI Stage 2 payload information is aggregated across two or more slots of the PSSCH, and wherein a number of resource elements (REs) used for the SCI Stage 2 payload information in a single slot is proportional to a PSSCH slot aggregation level used and a number of RE changes over successive slots for a transmission of the SCI Stage 2 payload information;

transmit SCI Stage 1 information on a Physical Sidelink Control Channel (PSCCH), wherein the SCI Stage 1 information indicates the resource mapping for the SCI Stage 2 payload information to the PSSCH;

perform encoding and rate matching on the SCI Stage 2 payload information, wherein the rate matching comprises at least one shortening operation on the SCI Stage 2 payload information in a first slot of the two or more slots of the PSSCH and at least one puncturing operation on the SCI Stage 2 payload information in a second slot of the two or more slots of the PSSCH; and

transmit the SCI stage 2 payload information on the PSSCH to one or more wireless devices, after performing the encoding, the rate matching, and the determining the resource mapping.

7 . The wireless device of claim 6 , wherein the wireless device is further configured to:

attach and distribute cyclic redundancy check (CRC) information to the payload information;

scramble the encoded and rate matched payload information; and

perform modulation on the scrambled payload information.

8 . The wireless device of claim 7 , wherein the encoding comprises a polar encoding operation.

9 . The wireless device of claim 7 , wherein the scrambling comprises using a same scrambling sequence over at least two of the aggregated two or more slots.

10 . The wireless device of claim 7 , wherein the scrambling comprises using a different scrambling sequence over at least two of the aggregated two or more slots.

11 . The wireless device of claim 6 , wherein determining the resource mapping for the SCI Stage 2 payload information comprises using a same resource mapping over at least two of the aggregated two or more slots.

12 . The wireless device of claim 6 , wherein determining the resource mapping for the SCI Stage 2 payload information comprises using a different resource mapping over at least two of the aggregated two or more slots.

13 . An integrated circuit, comprising circuitry configured to cause a wireless device to:

obtain sidelink control information (SCI) Stage 2 payload information;

determine a resource mapping for the SCI Stage 2 payload information to a Physical Sidelink Shared Channel (PSSCH), wherein the SCI Stage 2 payload information is aggregated across two or more slots of the PSSCH, and wherein a number of resource elements (REs) used for the SCI Stage 2 payload information in a single slot is proportional to a PSSCH slot aggregation level used and a number of RE changes over successive slots for a transmission of the SCI Stage 2 payload information;

transmit SCI Stage 1 information on a Physical Sidelink Control Channel (PSCCH), wherein the SCI Stage 1 information indicates the resource mapping for the SCI Stage 2 payload information to the PSSCH;

perform encoding and rate matching on the SCI Stage 2 payload information, wherein the rate matching comprises at least one shortening operation on the SCI Stage 2 payload information in a first slot of the two or more slots of the PSSCH and at least one puncturing operation on the SCI Stage 2 payload information in a second slot of the two or more slots of the PSSCH; and

transmit the SCI stage 2 payload information on the PSSCH to one or more wireless devices, after performing the encoding, the rate matching, and the determining the resource mapping.

14 . The integrated circuit of claim 13 , wherein the integrated circuit is further configured to cause the wireless device to:

attach and distribute cyclic redundancy check (CRC) information to the payload information;

scramble the encoded and rate matched payload information; and

perform modulation on the scrambled payload information.

15 . The integrated circuit of claim 14 , wherein the encoding comprises a polar encoding operation.

16 . The integrated circuit of claim 15 , wherein a same polar encoded and rate matched bits are transmitted in each of the aggregated two or more slots.

17 . The integrated circuit of claim 15 , wherein different polar encoded and rate matched bits are transmitted over at least two of the aggregated two or more slots.

18 . The integrated circuit of claim 14 , wherein the scrambling comprises using a different scrambling sequence over at least two of the aggregated two or more slots.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2021
From: ZHANG, YUSHU; YE, CHUNXUAN; ZHANG, DAWEI; HU, HAIJING; SUN, HAITONG; ZENG, WEI; WU, ZHIBIN
To: APPLE INC.
Reel/Frame 057596/0251 →
Continuity (1)
Related Publication 20230239899A1 · Jul 27, 2023
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