Method and device for transmitting S-SSB in NR V2X

1. A method for receiving, by a first apparatus, a sidelink (SL) synchronization signal block (SSB), the method comprising:

receiving an SL SSB from second apparatus,

wherein the SL SSB includes a first primary synchronization signal (PSS) symbol and a second PSS symbol,

wherein a first m-sequence is mapped to the first PSS symbol or the second PSS symbol, and

wherein a second m-sequence is mapped to a symbol to which the first m-sequence is not mapped among the first PSS symbol and the second PSS symbol; and

obtaining bit information based on an order in which the first m-sequence and the second m-sequence are mapped to the first PSS symbol and the second PSS symbol.

2. The method of claim 1 , wherein based on the mapping of the first m-sequence to the first PSS symbol and the mapping of the second m-sequence to the second PSS symbol, the bit information is obtained as 1, and

wherein based on the mapping of the first m-sequence to the second PSS symbol, and the mapping of the second m-sequence to the first PSS symbol, the bit information is obtained as 0.

3. The method of claim 1 , wherein the first m-sequence and the second m-sequence are generated based on a third m-sequence, and

wherein the third m-sequence includes a second sequence related to generation of a gold sequence included in the SSS symbol.

4. The method of claim 1 , wherein the bit information obtained based on an order in which the first m-sequence and the second m-sequence are mapped to the first PSS symbol and the second PSS symbol includes information related to sidelink synchronization signal (SLSS) identifier (ID).

5. The method of claim 1 , wherein the SL SSB includes a PSBCH,

wherein the PSBCH includes a plurality of DM-RSs,

wherein the plurality of DM-RSs are included in each different subcarrier,

wherein each of the subcarriers is in the same symbol, and

wherein a constant first frequency interval exists between each of the subcarriers.

6. The method of claim 5 , wherein the plurality of DM-RSs are included repeatedly in the PSBCH at regular time intervals.

7. The method of claim 6 , wherein each DM-RS repeatedly included in the PSBCH at the regular time interval is included in a subcarrier related to a frequency which is added by a regular second frequency interval from a frequency of each of the subcarriers including each of the DM-RS before the regular time interval whenever the respective DM-RS is repeatedly included in the PSBCH.

8. The method of claim 1 , wherein the first m-sequence is the same as the second m-sequence.

9. The method of claim 8 , wherein the first m-sequence is generated based on a first cyclic shift and a second cyclic shift, and

wherein the first cyclic shift differs from the second cyclic shift by 63 or 64.

10. The method of claim 9 , wherein the SL SSB includes a secondary synchronization signal (SSS) symbol, and

wherein the first m-sequence is generated using an initial value related to generation of the SSS symbol.

11. The method of claim 1 , wherein the first m-sequence is not identical to the second m-sequence.

12. The method of claim 11 , wherein the first m-sequence is generated based on a first cyclic shift and a second cyclic shift,

wherein the second m-sequence is generated based on a third cyclic shift and a fourth cyclic shift, and

wherein the first cyclic shift, the second cyclic shift, the third cyclic shift, and the fourth cyclic shift are different cyclic shifts selected from among four cyclic shifts that divide the length of the entire cyclic shift into quarters.

13. The method of claim 12 , wherein the SL SSB includes a SSS symbol, and

wherein the first m-sequence and the second m-sequence are generated using an initial value related to generation of the SSS symbol.

14. A first apparatus for performing wireless communication, the first apparatus comprising:

one or more memories storing instructions;

one or more transceivers; and

one or more processors connected to the one or more memories and the one or more transceivers, wherein the one or more processors execute the instructions to:

receive an SL SSB from second apparatus,

wherein the SL SSB includes a first primary synchronization signal (PSS) symbol and a second PSS symbol,

wherein a first m-sequence is mapped to the first PSS symbol or the second PSS symbol, and

wherein a second m-sequence is mapped to a symbol to which the first m-sequence is not mapped among the first PSS symbol and the second PSS symbol; and

obtain bit information based on an order in which the first m-sequence and the second m-sequence are mapped to the first PSS symbol and the second PSS symbol.

15. An apparatus configured to control a first user equipment (UE), the apparatus comprising:

one or more processors; and

one or more memories operably connectable to the one or more processors and storing instructions, wherein the one or more processors execute the instructions to:

receive an SL SSB from second UE,

wherein the SL SSB includes a first primary synchronization signal (PSS) symbol and a second PSS symbol,

wherein a first m-sequence is mapped to the first PSS symbol or the second PSS symbol, and

wherein a second m-sequence is mapped to a symbol to which the first m-sequence is not mapped among the first PSS symbol and the second PSS symbol; and

obtain bit information based on an order in which the first m-sequence and the second m-sequence are mapped to the first PSS symbol and the second PSS symbol.