IP Library Granted Patent US 11,846,682
Granted Patent B2
US 11,846,682 · App. 17/603,717 · Granted Dec 19, 2023

Method and device for avoiding abnormal signal oscillation in UVLO test

Inventor: Xin Sui (Jiangsu, CN)
Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
G01R31/40G01R19/10G01R19/16576G05F1/46
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Quick Facts
Patent No.
US 11,846,682
App. No.
17/603,717
Granted
Dec 19, 2023
Kind
B2
Abstract

A method and device for avoiding abnormal signal oscillation in UVLO test, applied to a power supply module, includes: a voltage detection module ( 301 ) detecting a voltage of an enable terminal of the power supply module during an under voltage lock out UVLO test; a difference calculation module ( 302 ) calculating a difference value between a detected voltage and a voltage trigger threshold of the enable terminal; upon a control module ( 303 ) determining that the difference value is below a preset first threshold, the control module increasing the voltage of the enable terminal during UVLO test via a voltage adjustment module. The application of the above solution of the present application can avoid abnormal signal oscillation in UVLO test.

Claims (19)

1. A method for avoiding abnormal signal oscillation in under voltage lock out (UVLO) test, applied to a power supply module, comprising:

detecting a voltage of an enable terminal of the power supply module during the UVLO test;

calculating a difference value between the voltage and a voltage trigger threshold of the enable terminal; and

in response to the difference value being below a preset first threshold, increasing the voltage of the enable terminal during the UVLO test.

2. The method for avoiding abnormal signal oscillation in UVLO test of claim 1 , wherein, the step of in response to the difference value being below the preset first threshold, increasing the voltage of the enable terminal during the UVLO test comprises:

in response to the difference value being below the preset first threshold, increasing the voltage of the enable terminal during the UVLO test by adjusting a voltage divider module connected to the enable terminal.

3. The method for avoiding abnormal signal oscillation in UVLO test of claim 2 , wherein, the voltage divider module comprises a first resistor module and a second resistor module, wherein, a first end of the first resistor module is configured for receiving an input voltage from the power supply module, a second end of the first resistor module is configured to be connected to a first end of the second resistor module and the enable terminal, and a second end of the second resistor module is grounded;

wherein the step of adjusting the voltage divider module connected to the enable terminal comprises:

increasing impedance of the second resistor module.

4. The method for avoiding abnormal signal oscillation in UVLO test of claim 3 , wherein, the first resistor module comprises a first resistor and the second resistor module comprises a first potentiometer.

5. The method for avoiding abnormal signal oscillation in UVLO test of claim 4 , wherein, the step of increasing the impedance of the second resistor module comprises:

moving, by a driving device, a brush of the first potentiometer to increase the impedance of the second resistor module.

6. The method for avoiding abnormal signal oscillation in UVLO test of claim 5 , wherein, the power supply module is a power supply module using MPQ8632GLE-6-Z.

7. The method for avoiding abnormal signal oscillation in UVLO test of claim 2 , wherein, the power supply module is a power supply module using MPQ8632GLE-6-Z.

8. The method for avoiding abnormal signal oscillation in UVLO test of claim 3 , wherein, the power supply module is a power supply module using MPQ8632GLE-6-Z.

9. The method for avoiding abnormal signal oscillation in UVLO test of claim 4 , wherein, the power supply module is a power supply module using MPQ8632GLE-6-Z.

10. The method for avoiding abnormal signal oscillation in UVLO test of claim 1 , wherein, in response to the difference value being below the preset first threshold, the method further comprises: outputting a prompt message.

11. The method for avoiding abnormal signal oscillation in UVLO test of claim 10 , wherein, the power supply module is a power supply module using MPQ8632GLE-6-Z.

12. The method for avoiding abnormal signal oscillation in UVLO test of claim 1 , wherein, the power supply module is a power supply module using MPQ8632GLE-6-Z.

Assignments (2)
LICENSE Recorded Jun 30, 2026
From: IEIT SYSTEMS CO., LTD
To: AIVRES SYSTEMS INC.
Reel/Frame 075857/0939 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2021
From: SUI, XIN
To: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
Reel/Frame 057810/0666 →
Priority Claims (1)
CN 201910299678.7 · Apr 15, 2019 · national
Continuity (1)
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