Cache allocation method and device, storage medium, and electronic device
A cache allocation method is provided. A core accesses a L3 cache when detecting a miss response from each of a L1 and a L2 cache accessed by the core through sending instruction fetching instructions configured to request L1 and L2 caches to return an instruction and data. The L1 cache is a private cache of the core, the L2 cache is a common cache corresponding to a core set including the core, the L3 cache is a common cache shared by core sets, and the miss response from the L2 cache carries network slice information. A planning unit in the L3 cache allocates the core sets to network slices, configures caches for the network slices according to the network slice information, and sends a hit response to the core. The hit response is configured to return data in a cache of a network slice corresponding to the core set.
1. A cache allocation method, comprising:
accessing, by a core, a level 3 cache in response to detecting a miss response from each of a level 1 cache and a level 2 cache, wherein the level 1 cache and the level 2 cache are accessed by the core through sending instruction fetching instructions; wherein the instruction fetching instructions are configured to request the level 1 cache and the level 2 cache that are accessed to return an instruction and data, the level 1 cache is a private cache of the core, the level 2 cache is a common cache corresponding to a core set including the core, the level 3 cache is a common cache shared by a plurality of core sets, and the miss response from the level 2 cache carries network slice information;
allocating, by a planning unit disposed in the level 3 cache, the plurality of core sets to a plurality of network slices and configuring, by the planning unit, corresponding caches for the plurality of network slices according to the network slice information; and
sending, by the planning unit, a hit response to the core, wherein the hit response is configured to return data in a cache of a network slice corresponding to the core set including the core.
2. The method according to claim 1 , wherein configuring, by the planning unit, the corresponding caches for the plurality of network slices comprises:
dividing, by the planning unit, the plurality of network slices into a plurality of network slice sets according to a preset division rule, wherein each of the plurality of network slice sets comprises at least one network slice;
setting, by the planning unit, flag information in each of the plurality of network slice sets; and
dividing, by the planning unit, a cache resource block for each network slice of a plurality of network slices in each of the plurality of network slice sets according to the flag information.
3. The method according to claim 2 , wherein the flag information comprises first flag information and second flag information, and dividing, by the planning unit, a cache resource block for each network slice of the plurality of network slices in each of the plurality of network slice sets according to the flag information comprises:
dividing, by the planning unit, the cache resource block for each network slice according to the first flag information and the second flag information, wherein the first flag information is configured to indicate a number of network slices in each of the plurality of network slice sets, and the second flag information is configured to flag address information corresponding to the network slices.
4. The method according to claim 3 , further comprising:
adjusting, by the planning unit, the address information and data information of each network slice according to priorities of the network slices in each of the plurality of network slice sets.
5. The method according to claim 4 , further comprising:
sending, by the core, an instruction fetching instruction to an external memory in response to detecting a miss response from the level 3 cache, wherein the level 3 cache is accessed by the core through sending the instruction fetching instruction, and receiving, by the core, an instruction fetching result fed back by the external memory; and
updating, by the planning unit, the address information and the data information according to the instruction fetching result.
6. The method according to claim 1 , wherein a number of instruction fetching instructions sent by the core is N when accessing caches, wherein N is a positive integer not less than 1.
7. A non-transitory storage medium storing a computer program, wherein the computer program is configured to perform a cache allocation method when executed; wherein the method comprises:
accessing a level 3 cache in response to detecting a miss response from each of a level 1 cache and a level 2 cache, wherein the level 1 cache and the level 2 cache are accessed by the core through sending instruction fetching instructions; wherein the instruction fetching instructions are configured to request the level 1 cache and the level 2 cache that are accessed to return an instruction and data, the level 1 cache is a private cache of the core, the level 2 cache is a common cache corresponding to a core set including the core, the level 3 cache is a common cache shared by a plurality of core sets, and the miss response from the level 2 cache carries network slice information;
allocating the plurality of core sets to a plurality of network slices and configuring corresponding caches for the plurality of network slices according to the network slice information; and
sending a hit response to the core, wherein the hit response is configured to return data in a cache of a network slice corresponding to the core set including the core.
8. The non-transitory storage medium according to claim 7 , wherein configuring the corresponding caches for the plurality of network slices comprises:
dividing the plurality of network slices into a plurality of network slice sets according to a preset division rule, wherein each of the plurality of network slice sets comprises at least one network slice;
setting flag information in each of the plurality of network slice sets; and
dividing a cache resource block for each network slice of a plurality of network slices in each of the plurality of network slice sets according to the flag information.
9. The non-transitory storage medium according to claim 8 , wherein the flag information comprises first flag information and second flag information, and dividing a cache resource block for each network slice of the plurality of network slices in each of the plurality of network slice sets according to the flag information comprises:
dividing the cache resource block for each network slice according to the first flag information and the second flag information, wherein the first flag information is configured to indicate a number of network slices in each of the plurality of network slice sets, and the second flag information is configured to flag address information corresponding to the network slices.
10. The non-transitory storage medium according to claim 9 , wherein the method further comprises:
adjusting the address information and data information of each network slice according to priorities of the network slices in each of the plurality of network slice sets.
11. The non-transitory storage medium according to claim 10 , wherein the method further comprises:
sending an instruction fetching instruction to an external memory in response to detecting a miss response from the level 3 cache, wherein the level 3 cache is accessed by the core through sending the instruction fetching instruction, and receiving an instruction fetching result fed back by the external memory; and
updating the address information and the data information according to the instruction fetching result.
12. The non-transitory storage medium according to claim 7 , wherein a number of instruction fetching instructions sent by the core is N when accessing caches, wherein N is a positive integer not less than 1.
13. An electronic device comprising a memory and a processor, wherein the memory stores a computer program which, when executed by the processor, causes the processor to perform a cache allocation method; wherein the method comprises:
accessing a level 3 cache in response to detecting a miss response from each of a level 1 cache and a level 2 cache, wherein the level 1 cache and the level 2 cache are accessed by the core through sending instruction fetching instructions; wherein the instruction fetching instructions are configured to request the level 1 cache and the level 2 cache that are accessed to return an instruction and data, the level 1 cache is a private cache of the core, the level 2 cache is a common cache corresponding to a core set including the core, the level 3 cache is a common cache shared by a plurality of core sets, and the miss response from the level 2 cache carries network slice information;
allocating the plurality of core sets to a plurality of network slices and configuring corresponding caches for the plurality of network slices according to the network slice information; and
sending a hit response to the core, wherein the hit response is configured to return data in a cache of a network slice corresponding to the core set including the core.
14. The electronic device according to claim 13 , wherein configuring the corresponding caches for the plurality of network slices comprises:
dividing the plurality of network slices into a plurality of network slice sets according to a preset division rule, wherein each of the plurality of network slice sets comprises at least one network slice;
setting flag information in each of the plurality of network slice sets; and
dividing a cache resource block for each network slice of a plurality of network slices in each of the plurality of network slice sets according to the flag information.
15. The electronic device according to claim 14 , wherein the flag information comprises first flag information and second flag information, and dividing a cache resource block for each network slice of the plurality of network slices in each of the plurality of network slice sets according to the flag information comprises:
dividing the cache resource block for each network slice according to the first flag information and the second flag information, wherein the first flag information is configured to indicate a number of network slices in each of the plurality of network slice sets, and the second flag information is configured to flag address information corresponding to the network slices.
16. The electronic device according to claim 15 , wherein the method further comprises:
adjusting the address information and data information of each network slice according to priorities of the network slices in each of the plurality of network slice sets.
17. The electronic device according to claim 16 , wherein the method further comprises:
sending an instruction fetching instruction to an external memory in response to detecting a miss response from the level 3 cache, wherein the level 3 cache is accessed by the core through sending the instruction fetching instruction, and receiving an instruction fetching result fed back by the external memory; and
updating the address information and the data information according to the instruction fetching result.
18. The electronic device according to claim 13 , wherein a number of instruction fetching instructions sent by the core is N when accessing caches, wherein N is a positive integer not less than 1.