Fractal calculating device and method, integrated circuit and board card
A fractal calculating device according to an embodiment of the present application is included in an integrated circuit device. The integrated circuit device includes a universal interconnect interface and other processing devices. The calculating device interacts with other processing devices to jointly complete a user specified calculation operation. The integrated circuit device may also comprise a storage device. The storage device is respectively connected with the calculating device and other processing devices and is used for data storage of the computing device and other processing devices.
1. A fractal calculating device comprising multiple layers of calculation units, wherein each layer of calculation units comprises:
a functional unit configured to perform tasks; and
a memory configured to store data related to the tasks,
wherein the multiple layers of calculation units include a root calculation unit, which is a topmost calculation unit, and a functional unit of the root calculation unit is configured to issue tasks,
wherein the multiple layers of calculation units include a middle layer of calculation units, wherein the functional unit of the middle layer of calculation units includes:
a plurality of fractal functional units configured to issue sub-tasks in the tasks and receive calculation results of the sub-tasks; and
a local functional unit configured to execute a local task among the tasks, wherein the local task includes reducing all the calculation results.
2. The fractal calculating device of claim 1 , wherein the multiple layers of calculation units include a leaf calculation unit, which is a unit in the lowest layer, and a functional unit of the leaf calculation unit includes an accelerator for calculating the sub-tasks to obtain calculation results.
3. The fractal calculating device of claim 2 , wherein the multiple layers of calculation units include a controller configured to assign the task or the sub-tasks to the functional unit.
4. The fractal calculating device of claim 3 , wherein the controller of the root calculation unit is configured to receive the task and send a local instruction to control the functional unit of the root calculation unit to execute the task.
5. The fractal calculating device of claim 3 , wherein the controller of the middle layer of calculation units is configured to:
generate fractal instructions and local instructions according to the task;
split the task into the sub-tasks and the local task, wherein each fractal functional unit corresponds to a sub-task; and
send a reduced calculation result to an upper of functional unit, wherein the fractal function unit issues the sub-tasks according to the fractal instructions, and the local functional unit executes the local task according to the local instructions.
6. The fractal calculating device of claim 3 , wherein the controller of the leaf calculation unit is configured to generate fractal instructions according to the task, and the accelerator calculates the sub-tasks according to the fractal instructions.
7. The fractal calculating device of claim 3 , wherein the controller of each layer of calculation unit copies data required by a lower layer of calculation units from a memory of this layer of calculation units to the memory of the lower layer of calculation units.
8. The fractal calculating device of claim 1 , further comprising a controller configured to assign the task to the functional unit.
9. The fractal calculating device of claim 1 , wherein the calculation units of each layer use a same instruction set architecture.
10. An integrated circuit device comprising the fractal calculating device of claim 1 .
11. A board card comprising the integrated circuit device of claim 10 .