IP Library › Granted Patent US 11,888,446
Granted Patent B2
US 11,888,446 · App. 17/607,943 · Granted Jan 30, 2024

Semiconductor device

Inventors: Kiyotaka Kimura (Kanagawa, JP); Takeya Hirose (Kanagawa, JP); Hidetomo Kobayashi (Kanagawa, JP); Takayuki Ikeda (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H03D7/12H01L27/1207H01L27/1225H01L27/1255H01L29/7869H01L29/78648H10B12/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,888,446
App. No.
17/607,943
Granted
Jan 30, 2024
Kind
B2
Abstract

A semiconductor device with a novel structure is provided. The semiconductor device includes a mixer circuit including a digital-analog converter circuit, a control circuit for controlling the digital-analog converter circuit, a power source control switch, and a plurality of Gilbert circuits. The plurality of Gilbert circuits each include an analog potential holding circuit for holding an analog potential output from the digital-analog converter circuit. The control circuit has a function of outputting a signal for controlling the analog potential holding circuit and the digital-analog converter circuit. The power source control switch has a function of stopping supply of a power source voltage to the control circuit in a period during which the analog potential held in the analog potential holding circuit is not updated. The analog potential holding circuit includes a first transistor. The first transistor includes a semiconductor layer including an oxide semiconductor in a channel formation region.

Claims (33)

1. A semiconductor device comprising:

a digital-analog converter circuit;

a control circuit;

a power source control switch;

an analog potential holding circuit including a first transistor; and

a plurality of Gilbert circuits,

wherein the analog potential holding circuit is configured to hold an analog potential output from the digital-analog converter circuit,

wherein the control circuit is configured to control the analog potential holding circuit and the digital-analog converter circuit,

wherein the power source control switch is configured to stop supply of a power source voltage to the control circuit in a period during which the analog potential held in the analog potential holding circuit is not updated, and

wherein the first transistor includes a semiconductor layer including an oxide semiconductor in a channel formation region.

2. The semiconductor device according to claim 1 ,

wherein the plurality of Gilbert circuits each include a second transistor, and

wherein the second transistor includes a semiconductor layer including silicon in a channel formation region.

3. The semiconductor device according to claim 2 ,

wherein the first transistor is stacked over a layer including the second transistor.

4. The semiconductor device according to claim 1 , further comprising an adder circuit and an amplifier circuit,

wherein the adder circuit is configured to add signals output from the plurality of Gilbert circuits, and

wherein the amplifier circuit is configured to amplify signals output from the adder circuit.

5. The semiconductor device according to claim 1 ,

wherein the digital-analog converter circuit, the control circuit, the power source control switch, the analog potential holding circuit, and the plurality of Gilbert circuits are included in a mixer circuit.

6. A semiconductor device comprising:

a digital-analog converter circuit;

an analog potential holding circuit including a first transistor; and

a Gilbert circuit including a second transistor,

wherein the analog potential holding circuit is configured to hold an analog potential output from the digital-analog converter circuit,

wherein the first transistor includes a semiconductor layer including an oxide semiconductor in a channel formation region, and

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor.

7. The semiconductor device according to claim 6 ,

wherein the second transistor includes a semiconductor layer including silicon in a channel formation region.

8. The semiconductor device according to claim 6 ,

wherein the first transistor is stacked over a layer including the second transistor.

9. The semiconductor device according to claim 6 ,

wherein the digital-analog converter circuit, the analog potential holding circuit, and the Gilbert circuit are included in a mixer circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2021
From: KIMURA, KIYOTAKA; HIROSE, TAKEYA; KOBAYASHI, HIDETOMO; IKEDA, TAKAYUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 057980/0175 →
Priority Claims (1)
JP 2019-087999 · May 8, 2019 · national
Continuity (1)
Related Publication 20220286090A1 · Sep 8, 2022