Display substrate, preparation method thereof, and display device
A display substrate includes an underlay substrate, a test signal access pin layer, and a signal access pin layer. The underlay substrate includes a display region and a border region at a periphery of the display region. The border region includes a signal access region at one side of the display region and at least one test signal access region adjacent to the signal access region. The test signal access pin layer is in the at least one test signal access region. The signal access pin layer is in the signal access region. A height difference between a surface of the test signal access pin layer away from the underlay substrate and a surface of the signal access pin layer away from the underlay substrate is greater than 0.
1 . A display substrate, comprising:
an underlay substrate, comprising a display region and a border region at a periphery of the display region, the border region comprising a fan-out region at one side of the display region, a signal access region and at least one test signal access region at one side of the fan-out region away from the display region, the at least one test signal access region being adjacent to the signal access region;
multiple sub-pixels in the display region;
multiple data lines in the display region, the multiple data lines being electrically connected with the multiple sub-pixels and arranged to provide data signals for the multiple sub-pixels;
multiple signal fan-out lines in the fan-out region, the multiple signal fan-out lines comprising multiple data fan-out lines connected with the multiple data lines in one-to-one correspondence;
a test signal access pin layer in the at least one test signal access region, the test signal access pin layer comprising multiple test signal access pins arranged to contact with a test probe of a testing device in an electronic test process; and
a signal access pin layer in the signal access region, the signal access pin layer comprising multiple signal access pins arranged to form bonding connections with a flexible printed circuit or an integrated circuit, the multiple signal access pins comprising multiple first signal access pins and multiple second signal access pins, the multiple first signal access pins being connected with multiple power lines in the fan-out region, at least part of the multiple second signal access pins being connected with the multiple signal fan-out lines,
wherein a height difference between a surface of the test signal access pin layer away from the underlay substrate and a surface of the signal access pin layer away from the underlay substrate is greater than 0.
2 . The display substrate according to claim 1 , wherein the multiple signal access pins are arranged abreast in parallel; and
the at least one test signal access region is at one or more sides of the multiple signal access pins in an arrangement direction of the multiple signal access pins.
3 . The display substrate according to claim 2 , wherein the multiple test signal access pins are, arranged in parallel with the multiple signal access pins.
4 . The display substrate according to claim 1 , further comprising a first insulating layer, arranged in the at least one test signal access region and located on a side of the test signal access pin layer close to the underlay substrate, wherein
a projection of the first insulating layer on the underlay substrate comprises a projection of the test signal access pin layer on the underlay substrate.
5 . The display substrate according to claim 4 , wherein the first insulating layer comprises multiple mutually isolated insulating portions in one-to-one correspondence with the multiple test signal access pins of the test signal access pin layer, and a projection of an insulating portion on the underlay substrate comprises a projection of a corresponding test signal access pin on the underlay substrate.
6 . The display substrate according to claim 5 , wherein the first insulating layer is an inorganic insulating layer.
7 . The display substrate according to claim 4 , wherein the first insulating layer is an inorganic insulating layer.
8 . The display substrate according to claim 1 , further comprising a second insulating layer, arranged in the test signal access region and the signal access region and located on sides of the test signal access pin layer and the signal access pin layer close to the underlay substrate, wherein a thickness of the second insulating layer in the test signal access region is greater than that in the signal access region.
9 . The display substrate according to claim 8 , wherein the second insulating layer is an inorganic insulating layer.
10 . The display substrate according to claim 1 , wherein the test signal access pin layer comprises multiple test signal access pin sub-layers which are stacked and mutually connected, and the signal access pin layer comprises multiple signal access pin sub-layers which are stacked and mutually connected; and the multiple test signal access pin sub-layers are in one-to-one correspondence with the multiple signal access pin sub-layers, and a test signal access pin sub-layer and a corresponding signal access pin sub-layer are in a same layer.
11 . The display substrate according to claim 1 , wherein a thickness of the test signal access pin layer is greater than that of the signal access pin layer.
12 . The display substrate according to claim 1 , wherein the height difference between the surface of the test signal access pin layer away from the underlay substrate and the surface of the signal access pin layer away from the underlay substrate is about 1,500 to 4,500 angstroms.
13 . The display substrate according to claim 1 , wherein the display region at least comprises a driving structure layer arranged on the underlay substrate;
the driving structure layer comprises a semiconductor layer, first gate metal layer, second gate metal layer, and source and drain metal layer which are sequentially arranged on the underlay substrate;
the test signal access pin layer comprises a first test signal access pin sub-layer and a second test signal access pin sub-layer which are stacked and mutually connected, and the signal access pin layer comprises a first signal access pin sub-layer and a second signal access pin sub-layer which are stacked and mutually connected;
the first test signal access pin sub-layer, the first signal access pin sub-layer, and the first gate metal layer are in a same layer; and
the second test signal access pin sub-layer, the second signal access pin sub-layer, and the source and drain metal layer are in a same layer.
14 . A display device, comprising the display substrate according to claim 1 .
15 . A preparation method of a display substrate, for preparing the display substrate according to claim 1 , the preparation method comprising:
forming a test signal access pin layer in a test signal access region of an underlay substrate, and forming a signal access pin layer in a signal access region of the underlay substrate, wherein a height difference between a surface of the test signal access pin layer away from the underlay substrate and a surface of the signal access pin layer away from the underlay substrate is greater than 0.
16 . The preparation method according to claim 15 , further comprising: forming a first insulating layer in the test signal access region before forming the test signal access pin layer, wherein a projection of the first insulating layer on the underlay substrate comprises a projection of the test signal access pin layer on the underlay substrate.
17 . The preparation method according to claim 15 , further comprising: forming a second insulating layer in the signal access region and the test signal access region before forming the test signal access pin layer and the signal access pin layer, wherein a thickness of the second insulating layer in the test signal access region is greater than that in the signal access region.
18 . The preparation method according to claim 15 , wherein a thickness of the test signal access pin layer is greater than that of the signal access pin layer.