Method for reducing influence of remote reference power noise on signal quality
A method for reducing influence of a remote reference power noise on signal quality is provided. A remote reference power plane connected to a power module is identified according to a schematic diagram of signal design, and a noised power plane is determined. A position of the noised power plane is found in a PCB, and whether the noised power plane is remote referenced by a high-speed signal is judged. Placement positions and number of connection capacitors are determined according to a layout and routing position of the high-speed signal and a width of the noised power plane. Two capacitors with fixed capacitance values are placed at the placement positions of the connection capacitors. Connection capacitors are added to a position of a noised remote reference power plane of a signal line for connecting the power plane and the ground.
1. A method for reducing influence of a remote reference power noise on signal quality of a printed circuit board (PCB), the method comprising steps of:
providing the PCB comprising at least one power plane connected to a power source and a power chip;
identifying a remote reference power plane connected to the power source according to a schematic diagram of signal design, determining a noised power plane, finding a position of the noised power plane in the PCB, and judging whether the noised power plane is remote referenced by a high-speed signal;
determining positions and a number of capacitors according to a layout and routing position of the high-speed signal and a width of the noised power plane; and
placing two capacitors with fixed capacitance values at the positions of the capacitors,
wherein the determining the noised power plane comprises measuring a voltage amplitude or a voltage oscillation where a voltage oscillates in a power plane directly connected to the power chip by an oscilloscope, and
wherein the determining of the noise power plane is based on:
an oscillating voltage of the voltage oscillation being greater than 10% of a voltage of the power chip,
the voltage amplitude jumping and a rising edge rate being greater than 0.3 V/ns, or
the voltage oscillation occurring during conversion and an oscillation frequency being between 100 kHz and 1 GHz.
2. The method according to claim 1 , wherein the determining the noised power plane is based on the oscillating voltage being greater than 10% of the voltage of the power chip.
3. The method according to claim 1 , wherein the determining the noised power plane is based on the voltage amplitude lumping and the rising edge rate being greater than 0.3 V/ns.
4. The method according to claim 1 , wherein the determining the positions and the number of capacitors according to the layout and routing position of the high-speed signal and the width of the noised power plane comprises:
placing, according to determined positions of a high-speed signal line and a remote reference plane, the capacitors on layer L 1 within a range of 80 mils perpendicular to a farthest end of the high-speed signal line, and placing a pair of the capacitors per 300 mils according to the width of the noised power plane, the capacitors being configured to connect the noised power plane and a ground.
5. The method according to claim 4 , further comprising:
placing the capacitors beside the high-speed signal line,
locating the capacitors on the layer L 1 for connecting the remote reference power plane and the ground,
locating the high-speed signal line on layer L 7 ,
locating the ground on layer L 6 , and
locating the remote reference power plane on layer L 8 .
6. The method according to claim 1 , wherein the two capacitors have fixed capacitance values of 0.01 μF and 0.1 μF, respectively.
7. The method according to claim 1 , wherein the determining the noised power plane is based on the voltage oscillation occurring during conversion and the oscillation frequency being between 100 kHz and 1 GHz.