Systems and methods using hybrid Boolean networks as physically unclonable functions
Systems, devices, and methods for generating a unique fingerprint are described herein. For example, an example integrated circuit (IC) chip includes a physically unclonable function (PUF) and an auxiliary circuit. The PUF is a hybrid Boolean network. Additionally, the auxiliary circuit is configured to receive a transient response enable signal.
1. An integrated circuit (IC) chip, comprising:
a physically unclonable function (PUF) comprising a hybrid Boolean network, wherein the hybrid Boolean network includes a first plurality of electronic devices, wherein each electronic device of the hybrid Boolean network is configured to implement a Boolean operation and includes clocked and un-clocked electronic devices; and
an auxiliary circuit, wherein the auxiliary circuit is configured to introduce a time delay and includes a second plurality of electronic devices, wherein each electronic device of the auxiliary circuit is configured to implement a copy operation, wherein the auxiliary circuit is configured to receive a transient response enable signal, and wherein the transient response enable signal is a transient response bit string used to provide cybersecurity to authenticate a device.
2. The IC chip of claim 1 , wherein a duration of the time delay is related to a characteristic time scale of the hybrid Boolean network.
3. The IC chip of claim 1 , wherein each electronic device of the auxiliary circuit is configured to implement a Boolean operation.
4. The IC chip of claim 3 , wherein the auxiliary circuit comprises a plurality of pairs of series-connected inverter gates.
5. The IC chip of claim 1 , wherein the hybrid Boolean network is configured as a modified random number generator.
6. The IC chip of claim 1 , further comprising a substrate, wherein the hybrid Boolean network and the auxiliary circuit are disposed on the substrate.
7. The IC chip of claim 6 , wherein the hybrid Boolean network and the auxiliary circuit are located in close physical proximity to each other on the substrate.
8. The IC chip of claim 6 , wherein the hybrid Boolean network and the auxiliary circuit are located adjacent to one another on the substrate.
9. The IC chip of claim 1 , further comprising a plurality of PUFs, each PUF comprising a respective hybrid Boolean network.
10. The IC chip of claim 9 , further comprising a combiner circuit configured to combine respective outputs of each of the PUFs.
11. The IC chip of claim 10 , wherein the combiner circuit comprises a PUF.
12. The IC chip of claim 1 , wherein the IC chip is a field-programmable gate array (FPGA).
13. The IC chip of claim 1 , wherein the IC chip is an application-specific IC (ASIC) chip.
14. The IC chip of claim 1 , further comprising a register, wherein the register is configured to receive the transient response enable signal via the auxiliary circuit.
15. The IC chip of claim 14 , wherein the register is configured to capture a response of the PUF.