IP Library › Granted Patent US 12,205,957
Granted Patent B2
US 12,205,957 · App. 17/626,765 · Granted Jan 21, 2025

Display substrate, manufacturing method thereof, and display device

Inventors: Xinguo Wu (Beijing, CN); Fengguo Wang (Beijing, CN); Hong Liu (Beijing, CN); Yu Feng (Beijing, CN); Liang Tian (Beijing, CN); Haidong Wang (Beijing, CN); Shicheng Song (Beijing, CN)
Assignees: Ordos Yuansheng Optoelectronics Co., Ltd.; BOE Technology Group Co., Ltd.
H01L27/1222H01L27/124H01L27/127
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Quick Facts
Patent No.
US 12,205,957
App. No.
17/626,765
Granted
Jan 21, 2025
Kind
B2
Abstract

The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a base substrate and a plurality of pixels arranged on the base substrate, each pixel includes a plurality of sub-pixels, and each sub-pixel includes a first active layer, a first gate insulation layer, a gate electrode, a second gate insulation layer, a second active layer, a first insulation layer, a source electrode and a drain electrode laminated one on another. The source electrode is connected with the first active layer through a via hole penetrating through the first insulation layer, the second gate insulation layer and the first gate insulation layer, and the source electrode and the drain electrode are connected with the second active layer through a via hole penetrating through the first insulation layer.

Claims (31)

1. A display substrate, comprising a base substrate and a plurality of pixels arranged on the base substrate, wherein each pixel comprises a plurality of sub-pixels, and each sub-pixel comprises a first active layer, a first gate insulation layer, a gate electrode, a second gate insulation layer, a second active layer, a first insulation layer, a source electrode and a drain electrode laminated one on another; wherein the source electrode is connected with the first active layer through a via hole penetrating through the first insulation layer, the second gate insulation layer and the first gate insulation layer; and the source electrode and the drain electrode are connected with the second active layer through a via hole penetrating through the first insulation layer;

wherein the display substrate further comprises a data line and a second insulation layer, wherein the data line is arranged at a side of the base substrate close to the first active layer, the second insulation layer is arranged between the data line and the first active layer, and the first active layer is connected with the data line through a via hole penetrating through the second insulation layer.

2. The display substrate according to claim 1 , wherein an orthographic projection of the second active layer onto the base substrate is arranged within a region of an orthographic projection of the first active layer onto the base substrate.

3. The display substrate according to claim 1 , wherein an orthographic projection of the first active layer onto the base substrate and an orthographic projection of the second active layer onto the base substrate are arranged within a region of an orthographic projection of the data line onto the base substrate.

4. The display substrate according to claim 1 , further comprising a third insulation layer, a pixel electrode, a fourth insulation layer and a common electrode, wherein the pixel electrode is connected with the drain electrode through a via hole penetrating through the third insulation layer, and the fourth insulation layer is arranged between the pixel electrode and the common electrode.

5. The display substrate according to claim 4 , wherein the third insulation layer is a planarization layer for isolating the source electrode and the drain electrode.

6. The display substrate according to claim 4 , wherein the fourth insulation layer is a passivation layer.

7. The display substrate according to claim 4 , wherein the pixel electrode and the common electrode are used to form a pixel driving electric field.

8. The display substrate according to claim 7 , wherein strip-shaped hollows are formed in the common electrode.

9. The display substrate according to claim 8 , wherein the pixel electrode and the common electrode are made of the same transparent conductive material.

10. The display substrate according to claim 1 , wherein a pixel density of the display substrate is greater than or equal to 1500 pixels per inch.

11. A display device, comprising the display substrate according to claim 1 .

12. The display device according to claim 11 , wherein the display device is an augmented reality display device or a virtual reality display device.

13. The display substrate according to claim 1 , wherein the first gate insulation layer and the second gate insulation layer are made of the same insulation material or different materials.

14. The display substrate according to claim 1 , wherein the materials of the second active layer and the first active layer are the same.

15. The display substrate according to claim 1 , wherein the source electrode and the drain electrode are made of the same or different metal materials as the gate electrode.

16. The display substrate according to claim 1 , wherein the materials of the second active layer and the first active layer are different.

17. A manufacturing method of a display substrate, comprising:

forming a base substrate; and

forming a first active layer, a first gate insulation layer, a gate electrode, a second gate insulation layer, a second active layer, a first insulation layer, a source electrode and a drain electrode on the base substrate in sequence;

wherein the source electrode is connected with the first active layer through a via hole penetrating through the first insulation layer, the second gate insulation layer and the first gate insulation layer; and the source electrode and the drain electrode are connected with the second active layer through a via hole penetrating through the first insulation layer;

wherein prior to forming the first active layer on the base substrate, the manufacturing method further comprises:

forming a data line on the base substrate; and

forming a second insulation layer on the data line and forming a via hole in the second insulation layer;

wherein the first active layer is connected with the data line through a via hole penetrating through the second insulation layer, and an orthographic projection of the first active layer onto the base substrate and an orthographic projection of the second active layer onto the base substrate are arranged within a region of an orthographic projection of the data line onto the base substrate.

18. The manufacturing method according to claim 17 , wherein an orthographic projection of the second active layer onto the base substrate is arranged within a region of an orthographic projection of the first active layer onto the base substrate.

19. The manufacturing method according to claim 17 , wherein after forming the source electrode and the drain electrode on the base substrate, the manufacturing method further comprises:

forming a third insulation layer and forming a via hole in the third insulation layer;

forming a pixel electrode connected with the drain electrode through a via hole penetrating through the third insulation layer;

forming a fourth insulation layer; and

forming a common electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2022
From: WU, XINGUO; WANG, FENGGUO; LIU, HONG; FENG, YU; TIAN, LIANG; WANG, HAIDONG; SONG, SHICHENG
To: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 058635/0982 →
Priority Claims (1)
CN 202010259736.6 · Apr 3, 2020 · national
Continuity (1)
Related Publication 20230018774A1 · Jan 19, 2023
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