Semiconductor device
A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.
1. A semiconductor device comprising:
a CPU; and
an accelerator,
wherein the accelerator comprises a first memory circuit, a driver circuit, and an arithmetic circuit,
wherein the first memory circuit comprises a first transistor,
wherein the first transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region,
wherein the driver circuit comprises a writing circuit and a reading circuit,
wherein the writing circuit is configured to switch data to be written to the first memory circuit to a binary or ternary voltage value in accordance with a switching signal, a writing control signal, and a data signal and outputting the voltage value,
wherein the reading circuit is configured to switch the voltage value to binary or ternary data corresponding to the voltage level retained in the first memory circuit in accordance with a first reference voltage and a second reference voltage and reading out the data,
wherein the driver circuit and the arithmetic circuit each comprise a second transistor,
wherein the second transistor comprises a semiconductor layer comprising silicon in a channel formation region, and
wherein the first transistor is stacked over the second transistor.
2. The semiconductor device according to claim 1 ,
wherein the arithmetic circuit performs a product-sum operation.
3. The semiconductor device according to claim 1 ,
wherein the metal oxide comprises In, Ga, and Zn.
4. The semiconductor device according to claim 1 ,
wherein the first transistor is electrically connected to a read bit line, and
wherein the read bit line is electrically connected to the arithmetic circuit through a wiring substantially perpendicular to a substrate with the second transistor.
5. A semiconductor device comprising:
a CPU; and
an accelerator,
wherein the accelerator comprises a first memory circuit and an arithmetic circuit,
wherein the first memory circuit comprises a first transistor,
wherein the first transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region,
wherein the arithmetic circuit comprises a second transistor,
wherein the second transistor comprises a semiconductor layer comprising silicon in a channel formation region,
wherein the CPU comprises a CPU core comprising a flip-flop with a backup circuit,
wherein the backup circuit comprises a third transistor,
wherein the third transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region, and
wherein the first transistor is stacked over the second transistor.
6. The semiconductor device according to claim 5 ,
wherein the backup circuit is configured to retain data retained in the flip-flop in a state where supply of a power supply voltage is stopped when the CPU does not operate.
7. The semiconductor device according to claim 5 ,
wherein the arithmetic circuit performs a product-sum operation.
8. The semiconductor device according to claim 5 ,
wherein the first transistor is electrically connected to a read bit line, and
wherein the read bit line is electrically connected to the arithmetic circuit through a wiring substantially perpendicular to a substrate with the second transistor.
9. A semiconductor device comprising:
a CPU; and
an accelerator,
wherein the accelerator comprises a first memory circuit, a driver circuit, and an arithmetic circuit,
wherein the first memory circuit comprises a first transistor,
wherein the first transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region,
wherein the driver circuit comprises a writing circuit and a reading circuit,
wherein the writing circuit is configured to switch data to be written to the first memory circuit to a binary or ternary voltage value in accordance with a switching signal, a writing control signal, and a data signal and outputting the voltage value,
wherein the reading circuit is configured to switch the voltage value to binary or ternary data corresponding to the voltage level retained in the first memory circuit in accordance with a first reference voltage and a second reference voltage and reading out the data,
wherein the arithmetic circuit comprises a second transistor,
wherein the second transistor comprises a semiconductor layer comprising silicon in a channel formation region,
wherein the CPU comprises a CPU core comprising a flip-flop with a backup circuit,
wherein the backup circuit comprises a third transistor,
wherein the third transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region, and
wherein the first transistor is stacked over the second transistor.
10. The semiconductor device according to claim 9 ,
wherein the backup circuit is configured to retain data retained in the flip-flop in a state where supply of a power supply voltage is stopped when the CPU does not operate.
11. The semiconductor device according to claim 9 ,
wherein the arithmetic circuit performs a product-sum operation.
12. The semiconductor device according to claim 9 ,
wherein the first transistor is electrically connected to a read bit line, and
wherein the read bit line is electrically connected to the arithmetic circuit through a wiring substantially perpendicular to a substrate with the second transistor.
13. The semiconductor device according to claim 1 ,
wherein the CPU and the accelerator are electrically connected to each other through a bus.
14. The semiconductor device according to claim 5 ,
wherein the CPU and the accelerator are electrically connected to each other through a bus.
15. The semiconductor device according to claim 9 ,
wherein the CPU and the accelerator are electrically connected to each other through a bus.