IP Library › Granted Patent US 12,334,875
Granted Patent B2
US 12,334,875 · App. 17/632,284 · Granted Jun 17, 2025

Semiconductor device and operation method thereof

Inventors: Kei Takahashi (Isehara, JP); Takayuki Ikeda (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H03F1/26H03F3/005H03F3/387H03F2200/372H10B12/00H10D30/6734H10D30/6755H10D86/423H10D86/481H10D86/60H10D87/00
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Quick Facts
Patent No.
US 12,334,875
App. No.
17/632,284
Granted
Jun 17, 2025
Kind
B2
Abstract

A semiconductor device includes a switch, a capacitor, a chopping circuit, and an amplifier. The amplifier includes a non-inverting input terminal, an inverting input terminal, an inverting output terminal, and a non-inverting output terminal. The semiconductor device, with use of the switch and the capacitor, has a function of sampling and holding a first potential and a second potential input in a first period. The chopping circuit is provided on each of the input terminal side and the output terminal side of the amplifier, and the first potential and the second potential are each input to either one of the non-inverting input terminal and the inverting input terminal in a second period. In a third period, the first potential and the second potential are each input to either one of the non-inverting input terminal and the inverting input terminal, which is different from the second period.

Claims (69)

1. A semiconductor device comprising:

a switch;

first and second capacitors;

first and second chopping circuits;

an amplifier;

first and second input terminals; and

first and second output terminals,

wherein the amplifier comprises a non-inverting input terminal, an inverting input terminal, an inverting output terminal, and a non-inverting output terminal,

wherein the semiconductor device electrically connects the first input terminal and one terminal of the first capacitor, electrically connects the second input terminal and one terminal of the second capacitor, directly connects the other terminal of the first capacitor and the first output terminal, and directly connects the other terminal of the second capacitor and the second output terminal in a first period,

wherein the first chopping circuit electrically connects the other terminal of the first capacitor and the non-inverting input terminal and electrically connects the other terminal of the second capacitor and the inverting input terminal in the first period,

wherein the second chopping circuit electrically connects the inverting output terminal and the first output terminal and electrically connects the non-inverting output terminal and the second output terminal in the first period,

wherein the semiconductor device electrically connects the one terminal of the first capacitor and the first output terminal and electrically connects the one terminal of the second capacitor and the second output terminal in a second period,

wherein the first chopping circuit electrically connects the other terminal of the first capacitor and the non-inverting input terminal and electrically connects the other terminal of the second capacitor and the inverting input terminal in the second period,

wherein the second chopping circuit electrically connects the inverting output terminal and the first output terminal and electrically connects the non-inverting output terminal and the second output terminal in the second period,

wherein the semiconductor device electrically connects the one terminal of the first capacitor and the first output terminal and electrically connects the one terminal of the second capacitor and the second output terminal in a third period,

wherein the first chopping circuit electrically connects the other terminal of the first capacitor and the inverting input terminal and electrically connects the other terminal of the second capacitor and the non-inverting input terminal in the third period, and

wherein the second chopping circuit electrically connects the non-inverting output terminal and the first output terminal and electrically connects the inverting output terminal and the second output terminal in the third period.

2. The semiconductor device according to claim 1 ,

wherein the switch, the first chopping circuit, and the second chopping circuit each comprise a transistor, and

wherein the transistor comprises a metal oxide in a channel formation region.

3. An operation method of a semiconductor device comprising:

a switch;

first and second capacitors;

first and second chopping circuits;

an amplifier;

first and second input terminals; and

first and second output terminals,

wherein the amplifier comprises a non-inverting input terminal, an inverting input terminal, an inverting output terminal, and a non-inverting output terminal,

wherein, in a first period, the semiconductor device electrically connects the first input terminal and one terminal of the first capacitor, electrically connects the second input terminal and one terminal of the second capacitor, directly connects the other terminal of the first capacitor and the first output terminal, and directly connects the other terminal of the second capacitor and the second output terminal,

wherein, in the first period, the first chopping circuit electrically connects the other terminal of the first capacitor and the non-inverting input terminal and electrically connects the other terminal of the second capacitor and the inverting input terminal,

wherein, in the first period, the second chopping circuit electrically connects the inverting output terminal and the first output terminal and electrically connects the non-inverting output terminal and the second output terminal,

wherein, in a second period, the semiconductor device electrically connects the one terminal of the first capacitor and the first output terminal and electrically connects the one terminal of the second capacitor and the second output terminal,

wherein, in the second period, the first chopping circuit electrically connects the other terminal of the first capacitor and the non-inverting input terminal and electrically connects the other terminal of the second capacitor and the inverting input terminal,

wherein, in the second period, the second chopping circuit electrically connects the inverting output terminal and the first output terminal and electrically connects the non-inverting output terminal and the second output terminal,

wherein, in a third period, the semiconductor device electrically connects the one terminal of the first capacitor and the first output terminal and electrically connects the one terminal of the second capacitor and the second output terminal,

wherein, in the third period, the first chopping circuit electrically connects the other terminal of the first capacitor and the inverting input terminal and electrically connects the other terminal of the second capacitor and the non-inverting input terminal, and

wherein, in the third period, the second chopping circuit electrically connects the non-inverting output terminal and the first output terminal and electrically connects the inverting output terminal and the second output terminal.

4. The operation method of a semiconductor device according to claim 3 ,

wherein the switch, the first chopping circuit, and the second chopping circuit each comprise a transistor, and

wherein the transistor comprises a metal oxide in a channel formation region.

5. A semiconductor device comprising:

first to sixth switches,

first and second capacitors,

first and second chopping circuits,

an amplifier,

first and second input terminals, and

first and second output terminals,

wherein the amplifier comprises a non-inverting input terminal, an inverting input terminal, an inverting output terminal, and a non-inverting output terminal,

wherein the first chopping circuit comprises first to fourth terminals,

wherein the second chopping circuit comprises fifth to eighth terminals,

wherein the first input terminal is electrically connected to one terminal of the first switch,

wherein the second input terminal is electrically connected to one terminal of the second switch,

wherein the other terminal of the first switch is electrically connected to one terminal of the third switch and one terminal of the first capacitor,

wherein the other terminal of the second switch is electrically connected to one terminal of the fourth switch and one terminal of the second capacitor,

wherein the other terminal of the first capacitor is electrically connected to one terminal of the fifth switch and the first terminal,

wherein the other terminal of the second capacitor is electrically connected to one terminal of the sixth switch and the second terminal,

wherein the third terminal is electrically connected to the non-inverting input terminal,

wherein the fourth terminal is electrically connected to the inverting input terminal,

wherein the inverting output terminal is electrically connected to the fifth terminal,

wherein the non-inverting output terminal is electrically connected to the sixth terminal,

wherein the seventh terminal is directly connected to the other terminal of the third switch, the other terminal of the fifth switch, and the first output terminal,

wherein the eighth terminal is directly connected to the other terminal of the fourth switch, the other terminal of the sixth switch, and the second output terminal,

wherein the first chopping circuit has a function of bringing the first terminal and the third terminal into a conduction state and a function of bringing the second terminal and the fourth terminal into a conduction state in a first period,

wherein the second chopping circuit has a function of bringing the fifth terminal and the seventh terminal into a conduction state and a function of bringing the sixth terminal and the eighth terminal into a conduction state in the first period,

wherein the first chopping circuit has a function of bringing the first terminal and the fourth terminal into a conduction state and a function of bringing the second terminal and the third terminal into a conduction state in a second period, and

wherein the second chopping circuit has a function of bringing the fifth terminal and the eighth terminal into a conduction state and a function of bringing the sixth terminal and the seventh terminal into a conduction state in the second period.

6. The semiconductor device according to claim 5 ,

wherein the first to sixth switches, the first chopping circuit, and the second chopping circuit each comprise a transistor, and

wherein the transistor comprises a metal oxide in a channel formation region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2022
From: TAKAHASHI, KEI; IKEDA, TAKAYUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 058861/0034 →
Priority Claims (1)
JP 2019-156546 · Aug 29, 2019 · national
Continuity (1)
Related Publication 20220302880A1 · Sep 22, 2022
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