IP Library Granted Patent US 11,799,430
Granted Patent B2
US 11,799,430 · App. 17/635,268 · Granted Oct 24, 2023

Semiconductor device and method for operating semiconductor device

Inventors: Kei Takahashi (Kanagawa, JP); Takeshi Aoki (Kanagawa, JP); Munehiro Kozuma (Kanagawa, JP); Takayuki Ikeda (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H03F3/45179H01L27/1207H03K5/2472H01L27/1211H02J7/0029
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Quick Facts
Patent No.
US 11,799,430
App. No.
17/635,268
Granted
Oct 24, 2023
Kind
B2
Abstract

A novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. In a semiconductor device, one of a source and a drain of a first transistor is electrically connected to one of a source and a drain of a second transistor and one of a source and a drain of a third transistor; the other of the source and the drain of the third transistor is electrically connected to a first output terminal; and the other of the source and the drain of the second transistor is electrically connected to a second output terminal. The semiconductor device has a function of outputting a comparison result of a signal supplied to a gate of the second transistor and a signal supplied to a gate of the third transistor, from the first output terminal and the second output terminal; and a function of changing the potential output from the first output terminal in accordance with the potential applied to a back gate of the first transistor.

Claims (35)

1. A method for operating a semiconductor device comprising a first output terminal, a second output terminal, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a capacitor,

wherein the first transistor comprises a back gate,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the first output terminal, and

wherein the other of the source and the drain of the second transistor is electrically connected to the second output terminal,

wherein one of a source and a drain of the fourth transistor is electrically connected to the first output terminal,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor,

wherein one electrode of the capacitor is electrically connected to the gate of the fourth transistor, and the other electrode is electrically connected to the first output terminal, and

wherein the semiconductor device is configured to output a comparison result of a signal supplied to a gate of the second transistor and a signal supplied to a gate of the third transistor, from the first output terminal and the second output terminal,

the operating method comprising:

a first step of applying a first potential to the back gate; and

a second step of applying a second potential to the back gate,

wherein the potential output from the first output terminal in the first step is lower than the potential output from the first output terminal in the second step, and

wherein the fifth transistor is in an off state in the first step and the second step.

2. The method for operating a semiconductor device, according to claim 1 ,

wherein the first transistor comprises an oxide semiconductor in a channel formation region.

3. The method for operating a semiconductor device, according to claim 1 ,

wherein a current flowing between the source and the drain of the first transistor is lower in the second step than in the first step.

4. The method for operating a semiconductor device, according to claim 1 ,

wherein a low potential signal is supplied to the other of the source and the drain of the first transistor, and

wherein high potential signals are supplied to the other of the source and the drain of the fourth transistor and the other of the source and the drain of the fifth transistor.

5. A semiconductor device comprising a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, and a selection circuit,

wherein the first transistor comprises a back gate,

wherein the selection circuit is configured to select one potential from two or more potentials and apply the potential to the back gate,

wherein a gate of the second transistor is electrically connected to the first input terminal,

wherein a gate of the third transistor is electrically connected to the second input terminal,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the third transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the first output terminal,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor, and

wherein one electrode of the capacitor is electrically connected to the gate of the fourth transistor, and the other electrode is electrically connected to the first output terminal,

wherein the other of the source and the drain of the third transistor is electrically connected to the first output terminal,

wherein the other of the source and the drain of the second transistor is electrically connected to the second output terminal,

wherein the first transistor comprises an oxide semiconductor in a channel formation region,

wherein the semiconductor device is configured to output a comparison result of a signal supplied to the first input terminal and a signal supplied to the second input terminal, from the first output terminal and the second output terminal; and

wherein the semiconductor device is configured to lower the potential output from the first output terminal by lowering a potential applied from the selection circuit to the back gate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2022
From: TAKAHASHI, KEI; AOKI, TAKESHI; KOZUMA, MUNEHIRO; IKEDA, TAKAYUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 059008/0431 →
Priority Claims (3)
JP 2019-152676 · Aug 23, 2019 · national
JP 2019-223352 · Dec 11, 2019 · national
JP 2020-005724 · Jan 17, 2020 · national
Continuity (1)
Related Publication 20220294402A1 · Sep 15, 2022