ELECTRONIC CIRCUITS AND CIRCUIT ELEMENTS
A method of manufacturing an electronic circuit comprising a first device and at least a second device is disclosed. The first device comprises a first terminal, a second terminal, and a first body of semiconductive material providing a semiconductive path between the first and second terminals, and the second device comprises a third terminal, a fourth terminal, and a second body of material providing a resistive or semiconductive current path between the third terminal and the fourth terminal. The method comprises: forming the first body; and forming the second body, wherein the first body comprises a first quantity of a metal oxide and the second body comprises a second quantity of said metal oxide. Corresponding electronic circuits are disclosed.
1 . A method of manufacturing an electronic circuit (or circuit module) ( 10000 ) comprising a first device ( 1 , 3000 ) and a second device ( 2 , 3000 ), the first device comprising a first terminal ( 11 , 3001 ), a second terminal ( 12 , 3002 ), and a first body ( 10 , 3010 ) of semiconductive material providing a semiconductive path between the first and second terminals, the second device ( 2 , 3000 ) comprising a third terminal ( 21 , 3001 ), a fourth terminal ( 22 , 3002 ), and a second body ( 20 , 3010 ) of material providing a resistive or semiconductive current path between the third terminal and the fourth terminal, the method comprising:
forming the first body ( 10 , 3010 ); and
forming the second body ( 20 , 3010 ), wherein the first body comprises a first quantity ( 100 , 3100 ) of a metal oxide and the second body comprises a second quantity ( 200 , 3100 ) of said metal oxide.
2 . A method in accordance with claim 1 , wherein forming the first body comprises forming said first quantity of said metal oxide, and forming the second body comprises forming said second quantity of said metal oxide.
3 . A method in accordance with claim 2 , wherein forming said first quantity comprises forming said first quantity ( 100 ) directly or indirectly on a first region ( 51 ) of a substrate (e.g. a flexible substrate), and forming said second quantity comprises forming said second quantity ( 200 ) directly or indirectly on a second region ( 52 ) of the substrate.
4 . A method in accordance with any one of claim 2 or 3 , wherein said forming of said first quantity comprises forming said first quantity ( 100 ) using a technique selected from a list comprising: physical deposition; physical vapour deposition (PVD); chemical deposition; chemical vapour deposition (CVD); atomic layer deposition (ALD); physical-chemical deposition; evaporation; sputtering; sol-gel techniques; chemical bath deposition; spray pyrolysis; plating techniques; pulsed laser deposition (PLD); solution processing; and spin coating.
5 . A method in accordance with any one of claims 2 to 4 , wherein said forming of said second quantity comprises forming said second quantity ( 200 ) using a technique selected from a list comprising: physical deposition; physical vapour deposition (PVD); chemical deposition; chemical vapour deposition (CVD); atomic layer deposition (ALD); physical-chemical deposition; evaporation; sputtering; sol-gel techniques; chemical bath deposition; spray pyrolysis; plating techniques; pulsed laser deposition (PLD); solution processing; and spin coating.
6 . A method in accordance with any one of claims 2 to 5 , wherein forming said first quantity comprises depositing said first quantity of said metal oxide.
7 . A method in accordance with any one of claims 2 to 6 , wherein forming said second quantity comprises depositing said second quantity of said metal oxide.
8 . A method in accordance with any one of claims 2 to 7 , wherein said forming of said first quantity is performed before said forming of said second quantity.
9 . A method in accordance with any one of claims 2 to 8 , wherein said forming of said first quantity is performed after said forming of said second quantity.
10 . A method in accordance with any one of claims 2 to 9 , wherein, said forming of said first quantity comprises forming (e.g. by depositing or otherwise forming) a first layer, film, or sheet ( 1001 ) of said metal oxide, said first layer, film, or sheet comprising said first quantity ( 100 ).
11 . A method in accordance with claim 10 , wherein forming the first body ( 10 ) comprises patterning the first layer, film, or sheet ( 1001 ).
12 . A method in accordance with any one of claims 2 to 11 , wherein forming of said second quantity comprises forming (e.g. by depositing or otherwise forming) a second layer, film, or sheet ( 2001 ) of said metal oxide, said second layer, film, or sheet comprising said second quantity ( 200 ).
13 . A method in accordance with claim 12 , wherein forming the second body ( 2 ) comprises patterning the second layer, film, or sheet ( 2001 ).
14 . A method in accordance with any preceding claim, further comprising doping said first body ( 10 ) of material with a first dopant to decrease or increase an electrical conductivity of said first body.
15 . A method in accordance with claim 14 , wherein doping said first body of material comprises forming said first quantity ( 100 ) on a source ( 71 ) of said first dopant.
16 . A method in accordance with claim 15 , further comprising providing said source ( 71 ) of said first dopant directly or indirectly on said first region ( 51 ) of the substrate.
17 . A method in accordance with any one of claims 14 to 16 , wherein doping said first body of material comprises forming a source of said first dopant on said first body of material.
18 . A method in accordance with any preceding claim, further comprising doping said second body ( 20 ) of material with a second dopant to increase or decrease an electrical conductivity of said second body.
19 . A method in accordance with claim 18 , wherein doping said second body of material comprises forming said second quantity ( 200 ) on a source ( 72 ) of said second dopant.
20 . A method in accordance with claim 19 , further comprising providing said source ( 72 ) of said second dopant directly or indirectly on said second region ( 52 ) of the substrate.
21 . A method in accordance with any one of claims 18 to 20 , wherein doping said second body of material comprises forming a source of said second dopant on said second body of material.
22 . A method in accordance with any preceding claim, further comprising processing said second quantity ( 200 ) of said metal oxide to increase or decrease an electrical conductivity of the second body.
23 . A method in accordance with claim 22 , wherein processing said second quantity comprises annealing at least a portion of said second quantity to increase or decrease its conductivity.
24 . A method in accordance with claim 22 or claim 23 , wherein processing said second quantity comprises exposing at least a portion of said second quantity to electromagnetic radiation.
25 . A method in accordance with claim 24 , further comprising providing said electromagnetic radiation from a lamp.
26 . A method in accordance with claim 24 , further comprising providing said electromagnetic radiation from a laser.
27 . A method in accordance with any one of claims 24 to 26 , further comprises shielding at least a portion of the first quantity ( 100 ) of said metal oxide from said electromagnetic radiation.
28 . A method in accordance with claim 27 , wherein said shielding comprises using said gate terminal ( 13 ) to shield said at least a portion of the first quantity ( 100 ) from said electromagnetic radiation.
29 . A method in accordance with any preceding claim, wherein each of the first and second bodies ( 10 , 20 ) comprises a respective layer, film, or sheet of said metal oxide, and each said respective layer, film, or sheet may have a thickness in the range 1 to 200 nm (for example 5 to 50 nm).
30 . A method in accordance with claim 29 , wherein each said respective layer, film, or sheet has the same thickness.
31 . A method in accordance with claim 29 or claim 30 , wherein each said respective layer, film, or sheet is flat (planar).
32 . A method in accordance with any preceding claim, further comprising forming the first and second bodies ( 10 , 20 ) in a common plane.
33 . A method in accordance with any one of claims 1 to 31 , further comprising forming the first body in a first plane and forming the second body in a second plane, said second plane being parallel to said first plane.
34 . A method in accordance with any preceding claim, wherein the second body has a sheet resistance value in the range 25 kOhm/sq to 20 MOhm/sq (e.g. in the range 50 kOhm/sq to 10 MOhm/sq).
35 . A method in accordance with any preceding claim, wherein each of the first and second bodies is substantially transparent to electromagnetic radiation in the range visible to the naked human eye.
36 . A method in accordance with any preceding claim, further comprising forming the first, second, third, and fourth terminals after forming the first and second bodies.
37 . A method in accordance with any one of claims 1 to 35 , further comprises forming the first, second, third, and fourth terminals before forming the first and second bodies, for example to form bottom contact devices.
38 . A method in accordance with any preceding claim, wherein said metal oxide is Indium Gallium Zinc Oxide, IGZO.
39 . A method in accordance with any preceding claim, wherein the first device is a transistor or a Schottky diode, and the second device is a resistor or a Schottky diode.
40 . A method in accordance with any preceding claim, wherein the circuit further comprises a third device ( 3 ) having fifth and sixth terminals ( 31 , 32 ) and a third body ( 30 ) of material providing a resistive or semiconductive current path between said fifth and sixth terminals, the method comprising forming said third body ( 30 ) of material, said third body comprising a third quantity ( 300 ) of said metal oxide.
41 . A method in accordance with claim 39 , further comprising doping or processing said third body differently from said second body, such that the second and third bodies exhibit different conductivities at room temperature.
42 . A method in accordance with claim 40 or claim 41 , wherein the third device ( 3 ) is a resistor or a Schottky diode.
43 . A method in accordance with any one of claims 40 to 42 , further comprising forming said third body before or after forming at least one of the first and second bodies.
44 . An electronic circuit (or circuit module) ( 10000 ) comprising a first device ( 1 , 3000 ) and a second device ( 2 , 3000 ),
the first device comprising a first terminal ( 11 , 3001 ), a second terminal ( 12 , 3002 ), and a first body ( 10 , 3010 ) of semiconductive material providing a semiconductive path between the first and second terminals,
the second device ( 2 , 3000 ) comprising a third terminal ( 21 , 3001 ), a fourth terminal ( 22 , 3002 ), and a second body ( 20 , 3010 )) of material providing a resistive or semiconductive current path between the third terminal and the fourth terminal,
wherein said first body ( 10 , 3010 ) of material comprises a metal oxide (e.g. comprises a first quantity ( 100 , 3100 ) of said metal oxide) and said second body ( 20 , 3010 ) of material comprises said metal oxide (e.g. comprises a second quantity ( 200 , 3100 ) of said metal oxide).
45 . An electronic circuit in accordance with claim 44 , wherein the first device is a transistor or a Schottky diode.
46 . An electronic circuit in accordance with any one of claim 44 or 45 , wherein the second device is a resistor or a Schottky diode.
47 . An electronic circuit in accordance with any one of claims 44 to 46 , further comprising at least one further device having a body comprising said metal oxide (e.g. comprising a third quantity of said metal oxide.
48 . An electronic circuit in accordance with claim 47 , wherein said further device is a transistor, resistor, or Schottky diode.
49 . An electronic circuit in accordance with any one of claims 44 to 48 , further comprising a substrate (e.g. a flexible substrate) arranged to support, directly or indirectly, each of said devices.
50 . A transistor ( 1 ) comprising: a source terminal ( 11 ), a drain terminal ( 12 ), a first body ( 10 ) of material providing a controllable semiconductive channel between the source and drain terminals, a first gate terminal ( 131 ) arranged on one side of (e.g. under) the first body ( 10 ), and a second gate terminal ( 132 ) arranged on an opposite side (e.g. above) the first body ( 10 ).
51 . A transistor in accordance with claim 50 , wherein the first gate terminal ( 131 ), first body ( 10 ), and the second gate terminal ( 132 ) are arranged as a stack in a first (i.e. nominally vertical) direction, with the first body ( 10 ) being arranged above the first gate terminal ( 131 ) and separated from the first gate terminal (in said first direction) by a first layer or body of dielectric material ( 41 ), the second gate terminal ( 132 ) being arranged above the first body ( 10 ) and separated from the first body ( 10 ) (in said first direction) by a second layer or body of dielectric material ( 42 ), and the source and drain terminals being arranged such that there is no overlap between projections of either gate terminal with projections of either the source or drain terminals onto a plane normal to said first direction (e.g. a horizontal plane, normal to the vertical direction).
52 . A transistor in accordance with claim 51 , wherein the first and second gate terminals are aligned and arranged to have the same projections as each other onto said plane.
53 . A transistor in accordance with claim 52 , wherein edges of the source and drain terminals are arranged to coincide with edges of the aligned gate terminals.
54 . A transistor in accordance with any one of claims 50 to 53 , wherein the first body ( 10 ) is provided by a first portion of a layer of metal oxide material, said first portion being arranged over said first gate terminal, and said source and drain terminals ( 11 , 12 ) are provided by respective portions of said layer of metal oxide material extending beyond edges of the first gate terminal.
55 . A transistor in accordance with claim 54 , wherein said respective portions have higher electrical conductivity than said first body.
56 . A method of manufacturing a dual-gate transistor, the method comprising: providing a lower gate terminal supported on a substrate; and using the lower gate terminal as a mask in the formation of an upper gate terminal aligned to the lower gate terminal.
57 . A method in accordance with claim 56 , further comprising: using the lower gate terminal as a mask in the formation of source and drain terminals aligned to the lower gate terminal.
58 . A method in accordance with claim 56 , further comprising: using the upper gate terminal as a mask in the formation of source and drain terminals aligned to the lower gate terminal.