FPGA dynamic reconfiguration method, apparatus, device and readable storage medium

1. A field programmable gate array (FPGA) dynamic reconfiguration method, comprising:

performing board support package (BSP) flat compilation on a target project to obtain a static region on an FPGA chip corresponding to the target project;

performing BSP generation and reconfiguration information compilation on the target project to obtain static information;

revising the static region using the static information to obtain reconfiguration compilation version projects that meet timing and correspond to different reconfiguration compilation parameters, respectively;

importing a preset heterogeneous acceleration kernel into the reconfiguration compilation version projects and then performing static compilation to obtain clock frequencies corresponding to the reconfiguration compilation version projects respectively; and

determining a target reconfiguration compilation version project with a clock frequency that meets performance requirements using the clock frequencies, and obtaining a dynamic reconfiguration compilation version project file using the target reconfiguration compilation version project.

2. The FPGA dynamic reconfiguration method according to claim 1 , wherein the performing BSP flat compilation on a target project to obtain a static region on an FPGA chip corresponding to the target project comprises:

performing BSP flat compilation on the target project under different flat compilation parameters to obtain spatial position information of layout and routing of interface Intellectual Property (IP) corresponding to the different flat compilation parameters respectively on the FPGA chip; and

determining the static region using the spatial position information according to static region division rules.

3. The FPGA dynamic reconfiguration method according to claim 1 , wherein the performing BSP generation and reconfiguration information compilation on the target project to obtain static information comprises:

performing BSP generation and reconfiguration information compilation on the target project under the different reconfiguration compilation parameters to obtain original reconfiguration compilation version projects corresponding to the different reconfiguration compilation parameters respectively; and

acquiring a critical path from the original reconfiguration compilation version projects, and using the critical path as the static information.

4. The FPGA dynamic reconfiguration method according to claim 3 , wherein the revising the static region using the static information to obtain reconfiguration compilation version projects that meet timing and correspond to different reconfiguration compilation parameters, respectively comprises:

correcting timing violations corresponding to the original reconfiguration compilation version projects and revising the static region using critical information to obtain the reconfiguration compilation version projects.

5. The FPGA dynamic reconfiguration method according to claim 1 , wherein the importing a preset heterogeneous acceleration kernel into the reconfiguration compilation version projects and then performing static compilation to obtain clock frequencies corresponding to the reconfiguration compilation version projects respectively comprises:

sequentially importing the preset heterogeneous acceleration kernel into each of the reconfiguration compilation version projects and then performing static compilation to obtain the clock frequencies corresponding to each of the reconfiguration compilation version projects, respectively, after being imported with different preset heterogeneous acceleration kernels.

6. The FPGA dynamic reconfiguration method according to claim 5 , wherein the determining a target reconfiguration compilation version project with a clock frequency that meets performance requirements using the clock frequencies, and obtaining a dynamic reconfiguration compilation version project file using the target reconfiguration compilation version project comprises:

calculating, using the clock frequencies, average clock frequencies corresponding to each of the reconfiguration compilation version projects after being imported with the different preset heterogeneous acceleration kernels;

determining a reconfiguration compilation version project corresponding to a maximum average clock frequency as the target reconfiguration compilation version project; and

acquiring the dynamic reconfiguration compilation version project file generated by the target reconfiguration compilation version project corresponding to the maximum average clock frequency.

7. The FPGA dynamic reconfiguration method according to claim 1 , wherein after the obtaining a dynamic reconfiguration compilation version project file using the target reconfiguration compilation version project, the method comprises:

dynamically reconfiguring the preset heterogeneous acceleration kernel in the FPGA chip on the basis of the dynamic reconfiguration compilation version project file.

8. A field programmable gate array (FPGA) dynamic reconfiguration device, comprising:

a memory configured to store a computer program; and

a processor configured to implement, when executing the computer program, the steps of a FPGA dynamic reconfiguration method, wherein the FPGA dynamic reconfiguration method comprises:

performing board support package (BSP) flat compilation on a target project to obtain a static region on an FPGA chip corresponding to the target project;

performing BSP generation and reconfiguration information compilation on the target project to obtain static information;

revising the static region using the static information to obtain reconfiguration compilation version projects that meet timing and correspond to different reconfiguration compilation parameters, respectively;

importing a preset heterogeneous acceleration kernel into the reconfiguration compilation version projects and then performing static compilation to obtain clock frequencies corresponding to the reconfiguration compilation version projects respectively; and

determining a target reconfiguration compilation version project with a clock frequency that meets performance requirements using the clock frequencies, and obtaining a dynamic reconfiguration compilation version project file using the target reconfiguration compilation version project.

9. The FPGA dynamic reconfiguration device according to claim 8 , wherein the performing BSP flat compilation on a target project to obtain a static region on an FPGA chip corresponding to the target project comprises:

performing BSP flat compilation on the target project under different flat compilation parameters to obtain spatial position information of layout and routing of interface Intellectual Property (IP) corresponding to the different flat compilation parameters respectively on the FPGA chip; and

determining the static region using the spatial position information according to static region division rules.

10. The FPGA dynamic reconfiguration device according to claim 8 , wherein the performing BSP generation and reconfiguration information compilation on the target project to obtain static information comprises:

performing BSP generation and reconfiguration information compilation on the target project under the different reconfiguration compilation parameters to obtain original reconfiguration compilation version projects corresponding to the different reconfiguration compilation parameters respectively; and

acquiring a critical path from the original reconfiguration compilation version projects, and using the critical path as the static information.

11. The FPGA dynamic reconfiguration device according to claim 10 , wherein the revising the static region using the static information to obtain reconfiguration compilation version projects that meet timing and correspond to different reconfiguration compilation parameters, respectively comprises:

correcting timing violations corresponding to the original reconfiguration compilation version projects and revising the static region using critical information to obtain the reconfiguration compilation version projects.

12. The FPGA dynamic reconfiguration device according to claim 8 , wherein the importing a preset heterogeneous acceleration kernel into the reconfiguration compilation version projects and then performing static compilation to obtain clock frequencies corresponding to the reconfiguration compilation version projects respectively comprises:

sequentially importing the preset heterogeneous acceleration kernel into each of the reconfiguration compilation version projects and then performing static compilation to obtain the clock frequencies corresponding to each of the reconfiguration compilation version projects, respectively, after being imported with different preset heterogeneous acceleration kernels.

13. The FPGA dynamic reconfiguration device according to claim 8 , wherein the determining a target reconfiguration compilation version project with a clock frequency that meets performance requirements using the clock frequencies, and obtaining a dynamic reconfiguration compilation version project file using the target reconfiguration compilation version project comprises:

calculating, using the clock frequencies, average clock frequencies corresponding to each of the reconfiguration compilation version projects after being imported with the different preset heterogeneous acceleration kernels;

determining a reconfiguration compilation version project corresponding to a maximum average clock frequency as the target reconfiguration compilation version project; and

acquiring the dynamic reconfiguration compilation version project file generated by the target reconfiguration compilation version project corresponding to the maximum average clock frequency.

14. The FPGA dynamic reconfiguration device according to claim 8 , wherein after the obtaining a dynamic reconfiguration compilation version project file using the target reconfiguration compilation version project, the processor is further configured to:

dynamically reconfiguring the preset heterogeneous acceleration kernel in the FPGA chip on the basis of the dynamic reconfiguration compilation version project file.

15. A non-transitory readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the steps of a FPGA dynamic reconfiguration method, wherein the FPGA dynamic reconfiguration method comprises:

performing board support package (BSP) flat compilation on a target project to obtain a static region on an FPGA chip corresponding to the target project;

performing BSP generation and reconfiguration information compilation on the target project to obtain static information;

revising the static region using the static information to obtain reconfiguration compilation version projects that meet timing and correspond to different reconfiguration compilation parameters, respectively;

importing a preset heterogeneous acceleration kernel into the reconfiguration compilation version projects and then performing static compilation to obtain clock frequencies corresponding to the reconfiguration compilation version projects respectively; and

determining a target reconfiguration compilation version project with a clock frequency that meets performance requirements using the clock frequencies, and obtaining a dynamic reconfiguration compilation version project file using the target reconfiguration compilation version project.

16. The non-transitory readable storage medium according to claim 15 , wherein the performing BSP flat compilation on a target project to obtain a static region on an FPGA chip corresponding to the target project comprises:

performing BSP flat compilation on the target project under different flat compilation parameters to obtain spatial position information of layout and routing of interface Intellectual Property (IP) corresponding to the different flat compilation parameters respectively on the FPGA chip; and

determining the static region using the spatial position information according to static region division rules.

17. The non-transitory readable storage medium according to claim 15 , wherein the performing BSP generation and reconfiguration information compilation on the target project to obtain static information comprises:

performing BSP generation and reconfiguration information compilation on the target project under the different reconfiguration compilation parameters to obtain original reconfiguration compilation version projects corresponding to the different reconfiguration compilation parameters respectively; and

acquiring a critical path from the original reconfiguration compilation version projects, and using the critical path as the static information.

18. The non-transitory readable storage medium according to claim 17 , wherein the revising the static region using the static information to obtain reconfiguration compilation version projects that meet timing and correspond to different reconfiguration compilation parameters, respectively comprises:

correcting timing violations corresponding to the original reconfiguration compilation version projects and revising the static region using critical information to obtain the reconfiguration compilation version projects.

19. The non-transitory readable storage medium according to claim 15 , wherein the importing a preset heterogeneous acceleration kernel into the reconfiguration compilation version projects and then performing static compilation to obtain clock frequencies corresponding to the reconfiguration compilation version projects respectively comprises:

sequentially importing the preset heterogeneous acceleration kernel into each of the reconfiguration compilation version projects and then performing static compilation to obtain the clock frequencies corresponding to each of the reconfiguration compilation version projects, respectively, after being imported with different preset heterogeneous acceleration kernels.