IP Library › Granted Patent US 12,074,124
Granted Patent B2
US 12,074,124 · App. 17/643,056 · Granted Aug 27, 2024

Integrated circuit package with integrated waveguide launcher

Inventors: Abdellatif Zanati (Hamburg, DE); Adrianus Buijsman (Nijmegen, NL); Dominik Xaver Simon (Munich, DE)
Assignee: NXP B.V.
H01L23/66H01L23/3107H01L23/49811H01L23/49822H01L23/552H01Q9/0407H05K1/0237H01L2223/6627H05K2201/10098
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Quick Facts
Patent No.
US 12,074,124
App. No.
17/643,056
Granted
Aug 27, 2024
Kind
B2
Abstract

An integrated circuit package comprising an encapsulant, a semiconductor die in the encapsulant the semiconductor die comprising a plurality of die terminals, an integrated waveguide launcher, wherein the integrated waveguide launcher is connected to one of the die terminals and a land grid array provided on a bottom surface of the package. The land grid array comprises a plurality of package terminals, each package terminal configured to be soldered to a printed circuit board, and an opening, wherein the opening is aligned with the integrated waveguide launcher.

Claims (44)

1. An integrated circuit package comprising:

an encapsulant;

a semiconductor die in the encapsulant, the semiconductor die comprising a plurality of die terminals;

an integrated waveguide launcher, wherein the integrated waveguide launcher is connected to one of the die terminals; and

a land grid array provided on a bottom surface of the package, the land grid array comprising:

a plurality of package terminals, each package terminal configured to be soldered to a connection;

a metal pad substantially surrounded by the plurality of package terminals; and

an opening formed in the metal pad, wherein the opening is aligned with the integrated waveguide launcher.

2. The integrated circuit package of claim 1 , comprising a shield arranged to reflect radiation from the waveguide launcher towards the waveguide opening.

3. The integrated circuit package of claim 2 , wherein the shield comprises a layer of silicon, or epoxy, or PCB laminate.

4. The integrated circuit package of claim 2 , wherein the shield is a periodically structured shield, or wherein the shield comprises a back-short.

5. The integrated circuit package of claim 1 , comprising a redistribution layer between the semiconductor die and the land grid array, wherein the waveguide launcher is provided in the redistribution layer.

6. The integrated circuit package of claim 5 , wherein the redistribution layer comprises a single metal layer.

7. The integrated circuit package of claim 2 , comprising a multi-layer laminate between the semiconductor die and the land grid array, wherein the shield is attached by a non-conductive adhesive to the multi-layer laminate.

8. A semiconductor device, comprising:

an integrated circuit comprising:

an encapsulant;

a semiconductor die in the encapsulant, the semiconductor die comprising a plurality of die terminals;

an integrated waveguide launcher, wherein the integrated waveguide launcher is connected to one of the die terminals; and

a land grid array provided on a bottom surface of the package, the land grid array comprising:

a plurality of package terminals, each package terminal configured to be soldered to a connection;

a metal pad substantially surrounded by the plurality of package terminals; and

an opening formed in the metal pad, wherein the opening is aligned with the integrated waveguide launcher; and

a printed circuit board, PCB, comprising a waveguide, wherein:

each package terminal is soldered to the PCB; and

the waveguide is aligned with the opening provided in the land grid array.

9. The semiconductor device of claim 8 , wherein the waveguide is a dielectric filled waveguide.

10. The semiconductor device of claim 8 , wherein the shape of the opening is configured to match the waveguide in the PCB.

11. The semiconductor device of any of claim 8 , wherein the PCB comprises a resonant patch antenna configured to match the land grid array to the waveguide.

12. The semiconductor device of claim 8 , further comprising a heat sink, wherein the heat sink is in contact with a top surface of the integrated circuit package.

13. The semiconductor device of claim 8 , further comprising:

an antenna feed network coupled to the PCB; and

an antenna array coupled to the antenna feed network.

14. An integrated circuit package comprising:

an encapsulant;

a semiconductor die in the encapsulant, the semiconductor die comprising a plurality of die terminals;

an integrated waveguide launcher, wherein the integrated waveguide launcher is connected to one of the die terminals; and

a land grid array provided on a bottom surface of the package, the land grid array comprising:

a plurality of package terminals, each package terminal configured to be soldered to a connection;

a metal pad substantially surrounded by the plurality of package terminals; and

an opening formed in the metal pad, wherein the opening is aligned with the integrated waveguide launcher.

15. The integrated circuit package of claim 14 , comprising a shield arranged to reflect radiation from the waveguide launcher towards the waveguide opening.

16. The integrated circuit package of claim 15 , wherein the shield comprises a layer of silicon, or epoxy, or PCB laminate.

17. The integrated circuit package of claim 14 , comprising a redistribution layer between the semiconductor die and the land grid array, wherein the waveguide launcher is provided in the redistribution layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2021
From: ZANATI, ABDELLATIF; BUIJSMAN, ADRIANUS; SIMON, DOMINIK XAVER
To: NXP B.V.
Reel/Frame 058324/0459 →
Priority Claims (1)
EP 20214555 · Dec 16, 2020 · regional
Continuity (1)
Related Publication 20220189894A1 · Jun 16, 2022
Cited By (2)
US 12,381,164 US 12,695,208