Adaptive control of meta-stability error bias in asynchronous successive approximation register ADC
Disclosed successive approximation register analog-to-digital converters (SAR ADCs) and conversion methods detect a statistical effect of meta-stability induced errors and limit the level of such errors. One illustrative integrated circuit chip includes: a SAR ADC that employs asynchronous bit cycles to convert a sequence of analog signal samples into a sequence of digital signal samples; and a detector that accelerates the asynchronous bit cycles when a meta-stability error bias exceeds a predetermined threshold. An illustrative analog-to-digital conversion method includes: converting a sequence of analog signal samples to a sequence of digital signal samples using a successive approximation register analog to digital converter (SAR ADC) with asynchronous bit cycles; deriving a meta-stability error bias from the sequence of digital signal samples; and accelerating the asynchronous bit cycles when the meta-stability error bias exceeds a predetermined threshold.
1. An integrated circuit chip that comprises:
a successive approximation register analog to digital converter (SAR ADC) that employs asynchronous bit cycles to convert a sequence of analog signal samples into a sequence of digital signal samples; and
a detector that accelerates the asynchronous bit cycles when a meta-stability error bias exceeds a predetermined threshold.
2. The chip of claim 1 , wherein the asynchronous bit cycles each include an adjustable delay, and wherein the detector accelerates the asynchronous bit cycles by reducing the adjustable delay.
3. The chip of claim 2 , wherein the adjustable delay is an interval between assertion of a Done signal and a beginning of a subsequent asynchronous bit cycle.
4. The chip of claim 1 , wherein the asynchronous bit cycles have an adjustable time limit, and wherein the detector accelerates the asynchronous bit cycles by reducing the adjustable time limit.
5. The chip of claim 1 , further comprising a retriggerable one shot that implements the adjustable time limit.
6. The chip of claim 1 , wherein the detector includes a counter to count a number of asserted least significant bits in a given number of said digital signal samples.
7. The chip of claim 6 , wherein the detector further includes a comparator to determine whether the number of asserted least significant bits varies from 50% of the given number by more than the predetermined threshold.
8. The chip of claim 7 , wherein the detector further includes a filter that adapts an adjustable component of the asynchronous bit cycles based on the comparator's output.
9. A method that comprises:
converting a sequence of analog signal samples to a sequence of digital signal samples using a successive approximation register analog to digital converter (SAR ADC) with asynchronous bit cycles;
deriving a meta-stability error bias from the sequence of digital signal samples; and
accelerating the asynchronous bit cycles when the meta-stability error bias exceeds a predetermined threshold.
10. The method of claim 9 , wherein the asynchronous bit cycles each include an adjustable delay, and wherein said accelerating includes reducing the adjustable delay.
11. The method of claim 10 , further comprising decelerating the asynchronous bit cycles when the meta-stability error bias falls below the predetermined threshold, wherein said decelerating includes increasing the adjustable delay.
12. The method of claim 9 , wherein the asynchronous bit cycles have an adjustable time limit, and wherein the detector accelerates the asynchronous bit cycles by reducing the adjustable time limit.
13. The method of claim 12 , further comprising decelerating the asynchronous bit cycles when the meta-stability error bias falls below the predetermined threshold, wherein said decelerating includes increasing the adjustable time limit.
14. The method of claim 9 , wherein said deriving includes counting a number of asserted least significant bits in a given number of said digital signal samples.
15. The method of claim 14 , wherein said deriving further includes comparing 50% of the given number minus the number of asserted least significant bits to the predetermined threshold.
16. The method of claim 15 , wherein said deriving further includes filtering a result of said comparing and adapting an adjustable component of the asynchronous bit cycles based on the filtered result.
17. A parallelized analog to digital converter that comprises:
a switch tree that distributes time-interleaved samples of an analog input signal to an array of successive approximation register analog to digital converters (SAR ADCs), each of the SAR ADCs converting their analog signal samples to digital signal samples using asynchronous bit cycles, the asynchronous bit cycles including an adjustable delay or having an adjustable time limit; and
a detector counting least significant bit assertions in a given number of digital signal samples to measure whether a meta-stability error bias exceeds a predetermined threshold.
18. The parallelized analog to digital converter of claim 17 , wherein the detector adapts the adjustable delay or adjustable time limit to limit the meta-stability error bias at the predetermined threshold.
19. The parallelized analog to digital converter of claim 18 , wherein the detector filters the detector's output to reduce the adjustable delay or adjustable time limit when the meta-stability error bias exceeds the predetermined threshold.
20. The parallelized analog to digital converter of claim 19 , wherein the detector uses the filtered output to increase the adjustable delay or adjustable time limit when the meta-stability error bias falls below the predetermined threshold.