Distribution of frequency budget in a processor
In an embodiment, a processor may include a core domain comprising a plurality of processing cores, an uncore domain comprising an internal network, and a processor power management circuit. The processor power management circuit may be to: receive scalability hint values from the processing cores; determine a total core gain and a total uncore gain based at least in part on the scalability hint values; and distribute a frequency budget between the core domain and the uncore domain based at least in part on the total core gain and the total uncore gain. Other embodiments are described and claimed.
1. A processor comprising:
a core domain comprising a plurality of processing cores;
an uncore domain comprising an internal network; and
a processor power management circuit to:
receive a plurality of scalability hint values from the plurality of processing cores;
determine a total core gain and a total uncore gain based at least in part on the plurality of scalability hint values; and
distribute a frequency budget between the core domain and the uncore domain based at least in part on the total core gain and the total uncore gain.
2. The processor of claim 1 , wherein each processing core comprises:
a core power management circuit to:
determine a plurality of metrics that indicate a current workload of the processing core; and
execute, using the plurality of metrics as inputs, a prediction algorithm to generate the plurality of scalability hint values.
3. The processor of claim 2 , wherein the plurality of metrics comprises:
instructions per cycle,
count of inactive cycles,
counts of queue occupancy for multiple thresholds,
count of prefetches in a cycle,
count of cache hits, and
count of cache misses.
4. The processor of claim 1 , wherein the internal network comprises a mesh network including a plurality of mesh stops.
5. The processor of claim 1 , wherein the plurality of scalability hint values comprises:
an instructions per second (IPS) value,
a core scalability (CS) value,
an uncore scalability (US) value, and
a quiesced core (QC) indication.
6. The processor of claim 5 , wherein the processor power management circuit is to:
for each of the plurality of processing cores, calculate a core gain value by multiplying the core scalability value, the IPS value, and a bin ratio; and
for each of the plurality of processing cores, calculate an uncore gain value by multiplying the uncore scalability value, the IPS value, and the bin ratio.
7. The processor of claim 6 , wherein the processor power management circuit is to:
calculate the total core gain as a sum of the core gain values for the plurality of processing cores; and
calculate the total uncore gain as a sum of the uncore gain values for the plurality of processing cores.
8. The processor of claim 6 , wherein the processor power management circuit is to:
generate, based at least on the total core gain and the total uncore gain, a workload hint to indicate a workload profile of the processing core; and
determine an uncore frequency based at least on the generated workload hint.
9. The processor of claim 5 , wherein the processor power management circuit is to:
determine a per core frequency budget based at least in part on the core scalability values for each of the plurality of processing cores.
10. A method comprising:
determining, for each processing core of a processor, a plurality of metrics indicating a current workload of the processing core, wherein the processor comprises a core domain and an uncore domain, and wherein the core domain comprises a plurality of processing cores;
executing by a power management circuit of the processor, using the plurality of metrics as inputs, a prediction algorithm to generate a plurality of scalability hint values;
determining, by the power management circuit, a total core gain and a total uncore gain based at least in part on the plurality of scalability hint values; and
distributing, by the power management circuit, a frequency budget between the core domain and the uncore domain based at least in part on the total core gain and the total uncore gain.
11. The method of claim 10 , wherein the plurality of scalability hint values comprises:
an instructions per second (IPS) value,
a core scalability (CS) value,
an uncore scalability (US) value, and
a quiesced core (QC) indication.
12. The method of claim 11 , further comprising:
for each of the plurality of processing cores, calculating a core gain value by multiplying the core scalability value, the IPS value, and a bin ratio; and
for each of the plurality of processing cores, calculating an uncore gain value by multiplying the uncore scalability value, the IPS value, and the bin ratio.
13. The method of claim 12 , further comprising:
calculating the total core gain as a sum of the core gain values for the plurality of processing cores; and
calculating the total uncore gain as a sum of the uncore gain values for the plurality of processing cores.
14. The method of claim 11 , further comprising:
determining a per core frequency budget based at least in part on the core scalability values for each of the plurality of processing cores.
15. The method of claim 10 , further comprising:
generating, based at least on the total core gain and the total uncore gain, a workload hint to indicate a workload profile of the processing core; and
determining an uncore frequency based at least on the generated workload hint.
16. The method of claim 10 , further comprising:
computing a ratio of the total core gain to the total uncore gain;
determining a budget distribution based on the ratio of the total core gain to the total uncore gain; and
distributing a frequency budget based on the determined budget distribution.
17. A system comprising:
a processor comprising:
a core domain comprising a plurality of processing cores;
an uncore domain comprising an internal network; and
a processor power management circuit to:
receive a plurality of scalability hint values from the plurality of processing cores;
determine a total core gain and a total uncore gain based at least in part on the plurality of scalability hint values; and
distribute a frequency budget between the core domain and the uncore domain based at least in part on the total core gain and the total uncore gain; and
a memory coupled to the processor.
18. The system of claim 17 , wherein the plurality of scalability hint values comprises an instructions per second (IPS) value, a core scalability (CS) value, an uncore scalability (US) value, and a quiesced core (QC) indication.
19. The system of claim 18 , wherein the processor power management circuit is to:
for each of the plurality of processing cores, calculate a core gain value by multiplying the core scalability value, the IPS value, and a bin ratio; and
for each of the plurality of processing cores, calculate an uncore gain value by multiplying the uncore scalability value, the IPS value, and the bin ratio.
20. The system of claim 19 , wherein the processor power management circuit is to:
calculate the total core gain as a sum of the core gain values for the plurality of processing cores; and
calculate the total uncore gain as a sum of the uncore gain values for the plurality of processing cores.