Amplifier bias circuit
Methods and apparatus for an amplifier including first and second transistors coupled in a stacked configuration with first and second current mirrors to provide respective bias signals to the amplifier transistors. A reference transistor is coupled to the first and second current mirrors for referencing the bias signals together.
1. A circuit, comprising:
an amplifier including first and second transistors coupled in a stacked configuration;
a first current mirror having a first control loop and a first mirror transistor coupled to a terminal of the first transistor to provide a first bias current, wherein the first current mirror includes the first mirror transistor, a first fixed current source, and a first follower transistor coupled to the first mirror transistor in a follower configuration;
a second current mirror having a second control loop and a second mirror transistor coupled to a terminal of the second transistor to provide a second bias current; and
a reference transistor coupled to the first and second current mirrors.
2. The circuit according to claim 1 , wherein the second current mirror includes the second mirror transistor, a second fixed current source, and a second follower transistor coupled to the second mirror transistor in a follower configuration.
3. The circuit according to claim 1 , wherein the reference transistor is coupled to the first mirror transistor and the second mirror transistor.
4. The circuit according to claim 1 , wherein the first control loop further includes at least one diode.
5. The circuit according to claim 1 , wherein an output of the first current mirror is configured to establish a source potential for a common gate reference of the second current mirror.
6. The circuit according to claim 5 , wherein the common gate reference of the second current mirror has a drain current from a second fixed current source.
7. The circuit according to claim 1 , wherein the amplifier comprises a depletion mode FET amplifier.
8. The circuit according to claim 1 , wherein the amplifier comprises an RF amplifier.
9. A method, comprising:
employing an amplifier including first and second transistors coupled in a stacked configuration;
employing a first current mirror having a first control loop and a first mirror transistor coupled to a terminal of the first transistor to provide a first bias current, wherein the first current mirror includes the first mirror transistor, a first fixed current source, and a first follower transistor coupled to the first mirror transistor in a follower configuration;
employing a second current mirror having a second control loop and a second mirror transistor coupled to a terminal of the second transistor to provide a second bias current; and
employing a reference transistor coupled to the first and second current mirrors.
10. The method according to claim 9 , wherein the second current mirror includes the second mirror transistor, a second fixed current source, and a second follower transistor coupled to the second mirror transistor in a follower configuration.
11. The method according to claim 9 , wherein the reference transistor is coupled to the first mirror transistor and the second mirror transistor.
12. The method according to claim 9 , wherein the first control loop further includes at least one diode.
13. The method according to claim 9 , wherein an output of the first current mirror is configured to establish a source potential for a common gate reference of the second current mirror.
14. The method according to claim 13 , wherein the common gate reference of the second current mirror has a drain current from a second fixed current source.
15. The method according to claim 9 , wherein the amplifier comprises a depletion mode FET amplifier.
16. The method according to claim 9 , wherein the amplifier comprises an RF amplifier.
17. A circuit comprising:
an input terminal configured to receive an RF input signal;
an output terminal configured to output an RF output signal;
an amplifier coupled to the input terminal and the output terminal, the amplifier including first and second transistors coupled in a stacked configuration;
a first current mirror having a first control loop and a first mirror transistor coupled to a terminal of the first transistor to provide a first bias current, wherein the first current mirror includes the first mirror transistor, a first fixed current source, and a first follower transistor coupled to the first mirror transistor in a follower configuration;
a second current mirror having a second control loop and a second mirror transistor coupled to a terminal of the second transistor to provide a second bias current; and
a reference transistor coupled to the first and second current mirrors.
18. The circuit of claim 17 , wherein an output of the first current mirror is configured to establish a source potential for a common gate reference of the second current mirror.
19. The circuit of claim 18 , wherein the common gate reference of the second current mirror has a drain current from a second fixed current source.
20. The circuit of claim 17 , wherein the second current mirror includes the second mirror transistor, a second fixed current source, and a second follower transistor coupled to the second mirror transistor in a follower configuration.