Negative-capacitance and ferroelectric field-effect transistor (NCFET and FE-FET) devices
Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack of the NCFET and FE-FET devices includes a non-ferroelectric interfacial layer formed over the semiconductor channel, and a ferroelectric gate dielectric layer formed over the interfacial layer. The ferroelectric gate dielectric layer is formed by inserting dopant-source layers in between amorphous high-k dielectric layers and then converting the alternating sequence of dielectric layers to a ferroelectric gate dielectric layer by a post-deposition anneal (PDA). The ferroelectric gate dielectric layer has adjustable ferroelectric properties that may be varied by altering the precisely-controlled locations of the dopant-source layers using ALD/PEALD techniques. Accordingly, the methods described herein enable fabrication of stable NCFET and FE-FET FinFET devices that exhibit steep subthreshold slopes.
1. A semiconductor device comprising:
a semiconductor region;
an interfacial layer disposed over the semiconductor region, the interfacial layer being a non-ferroelectric dielectric material;
a ferroelectric dielectric layer disposed over the interfacial layer, wherein the ferroelectric dielectric layer is an orthorhombic-phase polycrystalline doped hafnium oxide, wherein dopants in the ferroelectric dielectric layer are distributed non-uniformly within the ferroelectric dielectric layer, wherein a maximum peak of a dopant profile of the dopants in the ferroelectric dielectric layer is offset from an upper surface of the ferroelectric dielectric layer; and
a conductive material over the ferroelectric dielectric layer.
2. The semiconductor device of claim 1 , wherein a dopant profile of the dopants in the ferroelectric dielectric layer has at least two distinct convex regions.
3. The semiconductor device of claim 1 , wherein the maximum peak of the dopant profile of the dopants in the ferroelectric dielectric layer is offset from a lower surface of the ferroelectric dielectric layer.
4. The semiconductor device of claim 1 , wherein the interfacial layer and the ferroelectric dielectric layer form a dielectric stack, wherein a capacitance of the dielectric stack is negative for at least some range of gate bias.
5. The semiconductor device of claim 1 , wherein the ferroelectric dielectric layer has a thickness between 1 nm and 10 nm.
6. The semiconductor device of claim 1 , wherein a dopant profile of the dopants has a full width at half maximum (FWHM) distribution.
7. A semiconductor device comprising:
a semiconductor region, the semiconductor region comprising a channel region; and
a gate structure over the channel region, the gate structure comprising:
an interfacial layer disposed over the semiconductor region, the interfacial layer being a non-ferroelectric dielectric material;
a ferroelectric dielectric layer disposed over the interfacial layer, wherein the ferroelectric dielectric layer is an orthorhombic-phase polycrystalline doped hafnium oxide, wherein a maximum peak of the dopants in the ferroelectric dielectric layer is offset from an upper surface and a lower surface of the ferroelectric dielectric layer; and
a conductive material over the ferroelectric dielectric layer.
8. The semiconductor device of claim 7 , wherein the dopants comprise silicon, lanthanum, or zirconium.
9. The semiconductor device of claim 7 , wherein a dopant profile of the dopants in the ferroelectric dielectric layer has two convex regions.
10. The semiconductor device of claim 7 , wherein the dopants comprise silicon atoms, wherein a ratio of a number of dopant atoms incorporated in the ferroelectric dielectric layer to a total number of atoms in the ferroelectric dielectric layer is in a range between 0.5% and 30%.
11. The semiconductor device of claim 7 , wherein the dopants comprise lanthanum atoms, wherein a ratio of a number of dopant atoms incorporated in the ferroelectric dielectric layer to a total number of atoms in the ferroelectric dielectric layer is in a range between 0.5% and 50%.
12. The semiconductor device of claim 7 , wherein the dopants comprise zirconium atoms, wherein a ratio of a number of dopant atoms incorporated in the ferroelectric dielectric layer to a total number of atoms in the ferroelectric dielectric layer is in a range between 5% and 80%.
13. The semiconductor device of claim 7 , where a thickness of the ferroelectric dielectric layer is in a range between 1 nm and 10 nm.
14. The semiconductor device of claim 7 , wherein a dopant profile of the dopants has a full width at half maximum (FWHM) distribution.
15. A semiconductor device comprising:
a channel region;
source/drain regions on opposing sides of the channel region;
a dielectric layer over the source/drain regions; and
a gate structure extending through the dielectric layer, the gate structure being over the channel region, the gate structure comprising:
an interfacial layer disposed over the channel region, the interfacial layer being a non-ferroelectric dielectric material;
a ferroelectric dielectric layer disposed over the interfacial layer, wherein the ferroelectric dielectric layer is an orthorhombic-phase polycrystalline hafnium oxide doped with lanthanum, wherein a dopant profile of the lanthanum in the ferroelectric dielectric layer has a full width at half maximum (FWHM) distribution, wherein the dopant profile has a maximum peak concentration offset from an upper surface of the ferroelectric dielectric layer and from a lower surface of the ferroelectric dielectric layer; and
a conductive material over the ferroelectric dielectric layer.
16. The semiconductor device of claim 15 , wherein the dopants comprise lanthanum atoms, wherein a ratio of a number of dopant atoms incorporated in the ferroelectric dielectric layer to a total number of atoms in the ferroelectric dielectric layer is in a range between 0.5% and 50%.
17. The semiconductor device of claim 15 , where a thickness of the ferroelectric dielectric layer is in a range between 1 nm and 10 nm.
18. The semiconductor device of claim 15 , wherein the ferroelectric dielectric layer extends along sidewalls of the dielectric layer.
19. The semiconductor device of claim 15 , wherein an upper surface of the ferroelectric dielectric layer is level with an upper surface of the conductive material.
20. The semiconductor device of claim 15 , wherein the interfacial layer and the ferroelectric dielectric layer form a dielectric stack, wherein a capacitance of the dielectric stack is negative for at least some range of gate bias.