3D INTEGRATED CIRCUIT (3DIC) STRUCTURE

1 . A method comprising:

patterning a first opening in a first bonding layer of a first IC structure;

patterning a second opening in a second bonding layer of a second IC structure;

forming a connector in the first opening, wherein the connecter extends past a lateral surface of the first bonding layer;

forming a contact pad on a sidewall and a bottom surface of the second opening; and

bonding the first and the second IC structures, wherein bonding the first and the second IC structures comprises:

bonding the first bonding layer to the second bonding layer; and

bonding the connector to the contact pad, wherein the connector is partially disposed in the second opening.

2 . The method of claim 1 , wherein bonding the first and the second IC structures further comprises:

contacting the first bonding layer to the second bonding layer while heating the first IC structure at a first temperature; and

performing an annealing process at a second temperature on the first and the second IC structures after contacting the first bonding layer to the second bonding layer.

3 . The method of claim 2 , wherein the first temperature is lower than a melting temperature of the connector, and wherein the second temperature is at least as high as the melting temperature of the connector.

4 . The method of claim 1 , wherein after forming the contact pad, a lateral dimension of the second opening is greater than a lateral dimension of the connector in the first opening.

5 . The method of claim 1 , wherein forming the contact pad comprises forming the contact pad to surround a portion of the second opening, and wherein forming the connector comprises controlling an area of a portion of the connector extending past a lateral surface of the first bonding layer to be about 95% to about 100% of an area of the portion of the second opening surrounded by the contact pad.

6 . The method of claim 1 , wherein bonding the first and the second IC structures comprises forming an air gap in the second opening.

7 . The method of claim 1 , wherein patterning the first opening exposes a first conductive element in the first IC structure, and wherein patterning the second opening exposes a second conductive element in the second IC structure.

8 . The method of claim 1 , wherein forming the contact pad comprises:

forming a conformal conductive layer over the second bonding layer and in the second opening; and

performing a planarization to remove portions of the conformal conductive layer over the second bonding layer.

9 . A method comprising:

forming a first contact protruding from a first insulating layer on a first substrate;

forming a contact pad in a recess in a second insulating layer on a second substrate; and

bonding the first substrate and the second substrate by inserting the first contact protruding from the first insulating layer into the recess in the second insulating layer, wherein the first contact directly contacts the contact pad, wherein the bonding deforms first contact.

10 . The method of claim 9 , wherein the bonding further comprises bonding the first insulating layer to the second insulating layer.

11 . The method of claim 9 , wherein bonding comprises annealing.

12 . The method of claim 11 , wherein the annealing is performed at a temperature greater than a melting temperature of the first contact.

13 . The method of claim 9 , wherein after bonding a gap exists in the recess.

14 . The method of claim 9 , wherein after bonding the first contact completely covers a surface of the contact pad along a bottom of the recess.

15 . The method of claim 9 , wherein the first substrate comprises an integrated circuit, wherein the integrated circuit comprises a semiconductor substrate and an interconnect structure, wherein after bonding the interconnect structure is between the semiconductor substrate and the second substrate, further comprising:

after bonding, forming a through via through the semiconductor substrate to a metal interconnect in the interconnect structure.

16 . A method comprising:

forming a first insulating layer on a first IC structure, the first IC structure comprising a first substrate and a first interconnect structure on a first side of the first substrate;

forming a first insulating layer on the first interconnect structure;

forming a first opening in the first insulating layer, the first opening exposing a first conductive feature of the first interconnect structure;

forming a first contact in the first opening, the first contact extending further from the first substrate than a distal surface of the first insulating layer;

forming a second insulating layer on a second IC structure, the second IC structure comprising a second substrate and a second interconnect structure on a first side of the second substrate;

forming a second opening in the second insulating layer, the second opening exposing a second conductive feature of the second interconnect structure;

forming a second contact in the second opening, the second contact having a recessed upper surface; and

electrically coupling the first contact and the second contact by inserting the first contact into the recessed upper surface of the second contact, wherein the first contact contacts the second contact.

17 . The method of claim 16 , wherein electrically coupling the first contact and the second contact comprises annealing, wherein the annealing melts the first contact and bonds the first contact to the second contact.

18 . The method of claim 17 , wherein after annealing the first insulating layer overlaps the recessed upper surface of the second contact.

19 . The method of claim 18 , wherein after annealing an air gap is positioned between the first insulating layer and the second contact.

20 . The method of claim 16 , further comprising bonding the first insulating layer to the second insulating layer.