Bit line spacer structures including air gaps and method for forming the same

1. A method for forming a semiconductor device, comprising:

providing a base, on which multiple discrete conductive connection structures are formed;

forming sacrificial side walls on side walls of the conductive connection structures;

forming an outer side wall material layer on surfaces of the sacrificial side walls;

perforating the outer side wall material layer to form pinholes in the outer side wall material layer which expose the surfaces of the sacrificial side walls; wherein the perforating is performed by ion implantation; and when the ion implantation is performed, parts of the outer side wall material layer are removed by implanted ions through bombardment and/or chemical reaction, to form the pinholes in the outer side wall material layer which expose the surfaces of the sacrificial side walls;

removing the sacrificial side walls through the pinholes to form air gaps; and

forming a cover layer for sealing the pinholes.

2. The method for forming the semiconductor device of claim 1 , wherein a material of the outer side wall material layer is different from that of the sacrificial side walls.

3. The method for forming the semiconductor device of claim 2 , wherein a material of the sacrificial side walls is an oxide, and the outer side wall material layer is a nitride layer, a carbide layer or a carbonitride layer.

4. The method for forming the semiconductor device of claim 1 , wherein the material of the sacrificial side walls is silicon oxide, and the material of the outer side wall material layer is silicon nitride.

5. The method for forming the semiconductor device of claim 4 , wherein doped ions implanted by the ion implantation are BF 3 or AsH 3 , an implantation energy ranges from 1 KeV to 10 KeV, and an implantation angle ranges from 10 degrees to 45 degrees.

6. The method for forming the semiconductor device of claim 1 , wherein the sacrificial side walls are removed through the pinholes by a wet etching process.

7. The method for forming the semiconductor device of claim 6 , wherein a material of the sacrificial side walls is silicon oxide and an etching solution used in the wet etching process is a hydrofluoric acid solution.

8. The method for forming the semiconductor device of claim 1 , wherein the outer side wall material layer is formed on top surfaces of the conductive connection structures in addition to the surfaces of the sacrificial side walls.

9. The method for forming the semiconductor device of claim 1 , wherein the outer side wall material layer is only formed on the surfaces of the sacrificial side walls.

10. The method for forming the semiconductor device of claim 1 , further comprising: prior to forming the sacrificial side walls on the side walls of the conductive connection structures, forming inner side wall material layers on the side walls and top surfaces of the conductive connection structures; wherein after the inner side wall material layers are formed, the sacrificial side walls are formed on surfaces of the inner side wall material layers on the side walls of the conductive connection structures.

11. The method for forming the semiconductor device of claim 10 , wherein a material of the inner side wall material layers is different from that of the sacrificial side walls.

12. The method for forming the semiconductor device of claim 1 , wherein the cover layer is formed on a surface of the outer side wall material layer and top surfaces of the conductive connection structures, and the cover layer seals the pinholes.

13. The method for forming the semiconductor device of claim 11 , wherein the cover layer is formed by an atomic layer deposition process or plasma enhanced chemical vapor deposition.

14. The method for forming the semiconductor device of claim 1 , wherein the conductive connection structures are bit line structures of a memory.

15. The method for forming the semiconductor device of claim 1 , wherein the conductive connection structures are metal wire interconnection structures, plug structures, Damascene interconnection structures, or gate structures.

16. The method for forming the semiconductor device of claim 1 , wherein each of the pinholes is partially filled with the cover layer.

17. A method for forming a semiconductor device, comprising:

providing a base, on which multiple discrete conductive connection structures are formed;

forming sacrificial side walls on side walls of the conductive connection structures;

forming an outer side wall material layer on surfaces of the sacrificial side walls;

perforating the outer side wall material layer to form pinholes in the outer side wall material layer which expose the surfaces of the sacrificial side walls;

removing the sacrificial side walls through the pinholes to form air gaps; and

forming a cover layer for sealing the pinholes, wherein each of the pinholes is partially filled with the cover layer.