Vertical memory architecture
Methods, systems, and devices for a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.
1. A method, comprising:
forming a substrate;
forming a stack of materials on the substrate, the stack of materials comprising a first dielectric material and a second dielectric material in alternating layers;
etching the stack of materials to form a set of trenches and to expose a surface of the substrate;
depositing a first conductive material, a second conductive material, and an oxide material in a first subset of the set of trenches to form a plurality of selection elements, each selection element comprising a first pillar and a second pillar orthogonal to the substrate, the first pillar coupled with a bit line decoder and the second pillar coupled with a word line decoder;
depositing a chalcogenide material in a second subset of the set of trenches to form a plurality of storage elements, each storage element coupled with a selection element of the plurality of selection elements; and
depositing a third conductive material in a third subset of the set of trenches to form a plurality of plate lines coupled with a plate decoder, each storage element coupled with a plate line of the plurality of plate lines.
2. The method of claim 1 , further comprising:
depositing a sacrificial material in the first subset of the set of trenches and the second subset of the set of trenches based at least in part on etching the stack of materials; and
etching the sacrificial material to reform the first subset of the set of trenches, wherein depositing the first conductive material, the second conductive material, and the oxide material is based at least in part on etching the sacrificial material.
3. The method of claim 2 , further comprising:
depositing the second dielectric material in the first subset of the set of trenches based at least in part on etching the sacrificial material; and
etching the second dielectric material to form cavities in the first subset of the set of trenches centered on the sacrificial material in the second subset of the set of trenches, wherein the first conductive material, the second conductive material, and the oxide material are deposited in the cavities to form the plurality of selection elements.
4. The method of claim 2 , further comprising:
etching the sacrificial material to reform the second subset of the set of trenches based at least in part on forming the plurality of selection elements, wherein the chalcogenide material is deposited in the second subset of the set of trenches based at least in part on etching the sacrificial material.
5. The method of claim 1 , further comprising:
depositing a fourth conductive material in the first subset of the set of trenches to form a plurality of source contacts, each selection element comprising a source contact.
6. The method of claim 1 , further comprising:
depositing a fourth conductive material in the second subset of the set of trenches to form a first plurality of electrodes and a second plurality of electrodes, each storage element contacting a first electrode of the first plurality of electrodes and a second electrode of the second plurality of electrodes.
7. The method of claim 6 , wherein:
each electrode of the first plurality of electrodes contacts a selection element of the plurality of selection elements; and
each electrode of the second plurality of electrodes contacts a plate line of the plurality of plate lines.
8. The method of claim 1 , wherein an activation voltage of each selection element is less than a threshold voltage of the chalcogenide material.
9. The method of claim 1 , wherein:
a channel of each selection element comprises the first conductive material and is coupled with a bit line via a source contact; and
a gate contact of each selection element comprises the second conductive material in contact with the oxide material and is coupled with a word line.
10. The method of claim 1 , wherein:
the first conductive material comprises tungsten, polysilicon, or both; and
the second conductive material comprises tungsten, polysilicon, or both.