IP Library Granted Patent US 11,946,894
Granted Patent B2
US 11,946,894 · App. 17/651,254 · Granted Apr 2, 2024

Low noise amplifiers with feedback for nanopore applications

Inventor: Daniel Bedau (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
G01N27/228C12Q1/6869G01N27/226G01N33/48721H03F3/04H03F2200/294
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Quick Facts
Patent No.
US 11,946,894
App. No.
17/651,254
Granted
Apr 2, 2024
Kind
B2
Abstract

Disclosed herein are devices, systems, and methods that can improve the SNR of nanopore measurements by mitigating the effect of parasitic capacitance between the sense electrode and the counter electrode. In some embodiments, a feedback circuit is used to inject a charge into the sense electrode to at least partially cancel the parasitic capacitance between the sense electrode and the counter electrode. In some embodiments, bootstrapping of a signal from the amplifier output or from the sense electrode is used to inject a charge on the counter electrode to substantially cancel the parasitic capacitance.

Claims (48)

1. A system for detecting molecules, the system comprising:

a nanopore unit comprising at least one nanopore, at least one sense electrode, and a counter electrode;

an amplifier; and

a bootstrap circuit,

wherein:

the at least one sense electrode is configured to:

in cooperation with the counter electrode, detect a current associated with the at least one nanopore, and

provide the detected current to an input of the amplifier,

the amplifier is configured to provide, at an output of the amplifier, a signal representing the detected current, and

the bootstrap circuit is coupled to and situated between (a) the output of the amplifier and the counter electrode, or (b) the at least one sense electrode and the counter electrode.

2. The system recited in claim 1 , wherein the bootstrap circuit is frequency-selective.

3. The system recited in claim 1 , wherein the bootstrap circuit comprises at least one resistor and at least one capacitor.

4. The system recited in claim 1 , wherein the bootstrap circuit is configured to provide (i) a high-frequency voltage component to mitigate an effect of a parasitic capacitance between the at least one sense electrode and the counter electrode, and (ii) a low-frequency voltage component to bias the counter electrode.

5. The system recited in claim 1 , wherein the bootstrap circuit comprises a transistor and a capacitor.

6. The system recited in claim 5 , wherein the transistor is a source follower or an emitter follower.

7. The system recited in claim 5 , wherein the transistor is a bipolar junction transistor (BJT) or a junction-gate field effect transistor (JFET).

8. The system recited in claim 1 , wherein the amplifier is a first amplifier, and wherein the bootstrap circuit comprises a second amplifier.

9. The system recited in claim 1 , wherein:

the at least one nanopore comprises a plurality of nanopores,

the at least one sense electrode comprises a plurality of sense electrodes, each of the plurality of sense electrodes associated with a respective one of the plurality of nanopores, and

the counter electrode is shared by the plurality of nanopores,

and further comprising:

a multiplexer coupled to the plurality of sense electrodes and configured to select one of the plurality of sense electrodes to read an associated one of the plurality of nanopores;

a read circuit coupled to the multiplexer and configured to receive, from the multiplexer, a signal from the selected one of the plurality of sense electrodes;

a bias circuit coupled to the counter electrode;

a digitizer coupled to an output of the read circuit; and

control logic coupled to the digitizer.

10. The system recited in claim 9 , wherein the bootstrap circuit is frequency-selective.

11. The system recited in claim 9 , wherein the bootstrap circuit comprises at least one resistor and at least one capacitor.

12. The system recited in claim 9 , wherein the bootstrap circuit is configured to provide (i) a high-frequency voltage component to mitigate an effect of a parasitic capacitance between the selected one of the plurality of sense electrodes and the counter electrode, and (ii) a low-frequency voltage component to bias the counter electrode.

13. The system recited in claim 9 , wherein the bootstrap circuit comprises a transistor and a capacitor.

14. The system recited in claim 13 , wherein the transistor is a source follower or an emitter follower.

15. The system recited in claim 13 , wherein the transistor is a bipolar junction transistor (BJT) or a junction-gate field effect transistor (JFET).

16. The system recited in claim 9 , wherein the amplifier is a first amplifier, and wherein the bootstrap circuit comprises a second amplifier.

17. The system recited in claim 9 , wherein an input of the bootstrap circuit is from (a) an output of the read circuit, or (b) the selected one of the plurality of sense electrodes.

18. The system recited in claim 9 , wherein the plurality of nanopores is a first plurality of nanopores, the plurality of sense electrodes is a first plurality of sense electrodes, the counter electrode is a first counter electrode, the multiplexer is a first multiplexer, the read circuit is a first read circuit, the bootstrap circuit is a first bootstrap circuit, and the bias circuit is a first bias circuit, and further comprising:

a second plurality of nanopores;

a second plurality of sense electrodes, each of the second plurality of sense electrodes associated with a respective one of the second plurality of nanopores;

a second counter electrode shared by the second plurality of nanopores;

a second multiplexer coupled to the second plurality of sense electrodes and configured to select one of the second plurality of sense electrodes to read an associated one of the second plurality of nanopores;

a second read circuit coupled to the second multiplexer and configured to receive, from the second multiplexer, a signal from the selected one of the second plurality of sense electrodes;

a second bootstrap circuit coupled to the second counter electrode;

a second bias circuit coupled to the second counter electrode; and

a read multiplexer coupled to an output of the first read circuit and an output of the second read circuit and configured to provide a signal to the digitizer,

and wherein the control logic is further coupled to the first multiplexer and the second multiplexer and is configured to control the first multiplexer and the second multiplexer to select a single nanopore from among the first plurality of nanopores and the second plurality of nanopores.

19. The system recited in claim 18 , wherein:

an input of the first bootstrap circuit is from (a) an output of the first read circuit, or (b) the selected one of the first plurality of sense electrodes, and

an input of the second bootstrap circuit is from (i) an output of the second read circuit, or (ii) the selected one of the second plurality of sense electrodes.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2025
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 070313/0840 →
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0486 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069169/0572 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2022
From: BEDAU, DANIEL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059040/0164 →
Continuity (1)
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