Patent Assignment
Reel/Frame 069411/0486
SECURITY AGREEMENT (SUPPLEMENTAL)
Recorded: 2024-11-14
Received: 2024-11-14
Pages: 15
Assignor
SANDISK TECHNOLOGIES, INC.
Executed: 2024-10-30
Assignee
JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
10 S. DEARBORN L2, CHICAGO, IL, 60603, UNITED STATES
Covered Applications
(100)
STATE SKIP CODING FOR FRACTIONAL BIT-PER-CELL TECH NOLOGY TO IMPROVE DATA RETENTION
App. No. 18/921,761
→
Efficient Data Access for Accelerated Administrative Commands
App. No. 18/922,262
→
JOINT LDPC AND RAID DECODING SCHEME
App. No. 18/922,289
→
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING THERMALLY CONDUCTIVE AND INSULATING TRENCH FILL STRUCTURE AND METHODS FOR FORMING THE SAME USING LASER ANNEALING
App. No. 18/920,034
→
NONVOLATILE MEMORY WITH VOLTAGE OVERSHOOT MITIGATION
App. No. 18/919,469
→
Self-Tracking Dynamic Allocation of Free Chunks at L2P in Thin Provisioning
App. No. 18/919,573
→
THREE-DIMENSIONAL MEMORY DEVICE WITH TOP-CONTACT THROUGH-STACK CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/917,675
→
OFFSET CALIBRATION SCHEMES IN TIME-BASED 3D NAND-BASED VECTOR-MATRIX MULTIPLIER CIRCUIT
App. No. 18/917,095
→
THREE-DIMENSIONAL MEMORY DEVICE WITH TOP-CONTACT THROUGH-STACK CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/917,638
→
NONVOLATILE MEMORY WITH MULTI-CELL WEIGHT STRUCTURE
App. No. 18/916,844
→
NON-VOLATILE MEMORY WITH LOCATION DEPENDENT CONTROL GATE VOLTAGE
App. No. 18/916,496
→
Data Storage Device and Method to Access Logical Block Range
App. No. 18/916,686
→
ACTIVE AND PASSIVE ADAPTER FOR A MICROSD CARD
App. No. 18/914,512
→
Apparatus For Allowing The Protected mSets To Continue To Be Used During Control Sync (CS) On The Base Of Shadow uLayer
App. No. 18/914,949
→
OPERATING IN A WRITE THROUGH MODE TRANSITION WHILE MAINTAINING DATA INTEGRITY AFTER AN ABRUPT SHUTDOWN ON A STORAGE DEVICE
App. No. 18/914,526
→
TRANSIENT STATE MANAGEMENT OF AN INPUT/OUTPUT IMPACTED STORAGE DEVICE
App. No. 18/914,582
→
MEMORY DEVICE INCLUDING A PERFORATED DIELECTRIC BRIDGE LAYER AND METHOD FOR FORMING THE SAME
App. No. 18/909,661
→
Data Storage Device and Method for Maintaining a Weightage of Commands in a Plurality of Queue Layers
App. No. 18/909,057
→
SGS VOLTAGE IN UNSELECTED BLOCKS DURING PROGRAM
App. No. 18/905,292
→
MULTILAYER ELECTRODE DEVICES AND METHOD OF MAKING THE SAME
App. No. 18/904,344
→
NAND ACCELERATOR FOR VECTOR-VECTOR MULTIPLICATION
App. No. 18/905,088
→
Data Storage Device and Method for On-the-Fly Mathematical Processing of Data Read from the Data Storage Device
App. No. 18/904,260
→
Balanced Transfers on Interfaces
App. No. 18/904,530
→
Data Storage Device and Method for Avoiding Returning Zeros to a Host
App. No. 18/904,223
→
Data Storage Device and Method for Dynamic Bit-Error-Rate Estimation Scan (BES)
App. No. 18/903,283
→
ELECTRONIC DEVICE ENCLOSURE HAVING A PLURALITY OF SURFACE FEATURES
App. No. 18/902,041
→
PEER-TO-PEER SURVEILLANCE CAMERA ARCHITECTURE USING SHARED METADATA DATASTORE
App. No. 18/901,234
→
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MULTI-SURFACE SCHOTTKY SOURCE CONTACT AND METHODS FOR FORMING THE SAME
App. No. 18/897,891
→
APPARATUS AND METHODS FOR MODIFYING IMPEDANCES IN TIME-BASED VECTOR-MATRIX MULTIPLICATION CIRCUITS
App. No. 18/897,326
→
THRESHOLD VOLTAGE TRACKING TECHNIQUES FOR MEMORY DEVICES
App. No. 18/897,684
→
READ TECHNIQUES FOR NON-VOLATILE MEMORY
App. No. 18/897,714
→
WORD LINE ZONE ERASE TECHNIQUES FOR MEMORY DEVICES
App. No. 18/897,573
→
Data Storage Device and Method for Speculation-Driven Partial Shutdown
App. No. 18/897,295
→
REDUCED CURRENT SENSING TECHNIQUES
App. No. 18/897,505
→
EFFICIENT TRAINING METHOD FOR UNMATCHED DATA OUTPUT PATH IN NON-VOLATILE MEMORY
App. No. 18/896,420
→
PCIe LANE ADAPTER FOR ENABLING FLEXIBLE SWITCHING OF SPEED AND CAPACITY CONFIGURATIONS OF STORAGE DRIVES
App. No. 18/894,152
→
PRE-CHARGE UNSELECTED BLOCK WORD LINE BEFORE PROGRAM
App. No. 18/894,270
→
NON-VOLATILE MEMORY WITH NON-DISCHARGING READ
App. No. 18/894,550
→
SYNCHRONIZATION POINTS BASED PARAMETER TUNING IN A STORAGE DEVICE
App. No. 18/894,234
→
MANAGING TIME-CRITICAL COMMANDS IN A MULTI-CORE STORAGE DEVICE
App. No. 18/892,779
→
METAL CHLORIDE GAS GENERATION METHOD AND APPARATUS
App. No. 18/893,461
→
FASTER METHOD TO PREVENT HYBRID SINGLE LEVEL CELL DEFECTS IN SYSTEM
App. No. 18/891,932
→
BONDED ASSEMBLIES AND METHODS FOR FORMING THE SAME USING POLYMER-BASED HYBRID BONDING
App. No. 18/891,177
→
FAILSAFE POWER MANAGEMENT TO AVOID SHORT-CIRCUITING FROM WATER DAMAGE IN SOLID STATE DRIVE USING CONDUCTIVITY DETECTOR
App. No. 18/890,025
→
NUCLEIC ACID SEQUENCING BY SYNTHESIS USING MAGNETIC SENSOR ARRAYS
App. No. 18/888,896
→
CHARGE PUMP CIRCUIT CONFIGURATION IN NONVOLATILE MEMORY
App. No. 18/887,054
→
TECHNIQUE TO DETECT AN UNSELECTED SUB-BLOCK STATUS IN A MEMORY DEVICE
App. No. 18/887,730
→
TAMPER-RESISTANT MICROELECTRONIC CIRCUIT PACKAGES
App. No. 18/886,576
→
IN-PLACE ERASE TECHNIQUES FOR NONVOLATILE MEMORY DEVICES
App. No. 18/886,384
→
NON-VOLATILE MEMORY WITH VARIABLE ON PITCH
App. No. 18/886,398
→
DIE LEVEL FAILURE RECOVERY
App. No. 18/886,461
→
ENABLE OPEN SUB-BLOCK ERASE IN SUB-BLOCK MODE OPERATION
App. No. 18/883,214
→
GATE INDUCED DRAIN LEAKAGE ERASE WITH ADAPTIVE BIAS ON TOP DRAINSIDE SELECT GATE TRANSISTOR AND BOTTOM SOURCE-SIDE SELECT GATE TRANSISTOR
App. No. 18/883,219
→
CYCLING-AWARE ADAPTIVE PROGRAM VOLTAGE TUNING FOR PERFORMANCE IMPROVEMENT
App. No. 18/883,221
→
THREE-DIMENSIONAL MEMORY DEVICE WITH BACKSIDE GATE ELECTRODE AND METHODS OF FORMING THE SAME
App. No. 18/883,650
→
MULTILAYER ELECTRODE DEVICES AND METHOD OF MAKING THE SAME
App. No. 18/882,360
→
THROUGHPUT OPTIMIZED 3D NAND-BASED VECTOR-BY-MATRIX MULTIPLIER CIRCUIT
App. No. 18/830,759
→
MULTILAYER ELECTRODE DEVICES AND METHOD OF MAKING THE SAME
App. No. 18/882,410
→
Apparatus and Processes for Magnetic Detection of an Analyte
App. No. 18/830,920
→
DOUBLE MAGNETIC TUNNEL JUNCTION MAGNETORESISTIVE MEMORY DEVICE AND METHOD OF MAKING THEREOF
App. No. 18/882,112
→
MULTILAYER ELECTRODE DEVICES AND METHOD OF MAKING THE SAME
App. No. 18/882,390
→
Command Processing In Sequential Write Required Zone
App. No. 18/829,608
→
Dynamic Lane Allocation On Power Limited, Dual Port PCIe Device
App. No. 18/829,622
→
HOST INDEPENDENT CONTROL OF STORAGE DEVICES USING CONTROL DEVICES
App. No. 18/830,183
→
POWER ON DATA RETENTION MANAGEMENT WITH DYNAMIC ACTIVATION ENERGY TABLE FOR NON-VOLATILE MEMORIES
App. No. 18/830,257
→
STRUCTURES AND METHODS FOR ACCURATE SEGMENTING OF BAD BLOCKS OF NON-VOLATILE MEMORY
App. No. 18/827,981
→
SOT MRAM ARRAY INCLUDING SHARED BIT LINE CONNECTION VIA STRUCTURES AND METHOD OF MAKING THE SAME
App. No. 18/828,504
→
MITIGATING BIT LINE IR DROP IN 3D NAND NEURAL NETWORK ACCELERATOR
App. No. 18/826,542
→
AREA EFFICIENT 3D NAND-BASED VECTOR-MATRIX MULTIPLIER CIRCUIT WITH COMMON-MODE CURRENT CANCELLATION
App. No. 18/826,339
→
NON-VOLATILE MEMORY ARRAY WITH INTEGRATED MEMORY AND ACCESS TRANSISTORS AND METHOD OF MAKING THE SAME
App. No. 18/827,036
→
ADDRESS PATH ROUTING REDUCTION STRATEGY FOR NONVOLATILE MEMORY DECODERS
App. No. 18/825,487
→
MULTI-PLANE LEAKAGE DETECTION IN NONVOLATILE MEMORY
App. No. 18/825,432
→
SEMICONDUCTOR DEVICE WITH STRUCTURALLY REINFORCED CORNERS
App. No. 18/825,864
→
Data Storage Device and Method for Buffer Occupancy-Based Data Placement to Avoid Video Loss
App. No. 18/825,319
→
MULTI-PLANE NONVOLATILE MEMORY WITH SERIAL ENCODER AND DECODER CIRCUITS
App. No. 18/825,452
→
Host and Dual Write Method for Avoiding Data Loss When Writing to an External Data Storage Device
App. No. 18/825,264
→
BIPOLAR DECODERS FOR NONVOLATILE MEMORY WITH SPIKE ATTENUATION FOR THRESHOLD SELECTOR SWITCHES
App. No. 18/824,608
→
NON-VOLATILE MEMORY WITH ADJUSTABLE ERASE VOLTAGE
App. No. 18/824,083
→
THREE-DIMENSIONAL MEMORY DEVICE WITH SIDE-CONTACT THROUGH-STACK CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/824,214
→
MEMORY STRUCTURE WITH SECURE GLOBAL ERASE
App. No. 18/824,397
→
Configurable Arithmetic HW Accelerator
App. No. 18/823,094
→
Data Storage With Real Time Dynamic Clock Frequency Control
App. No. 18/823,112
→
Host Controlled Mitigation of Panic Situation
App. No. 18/819,515
→
Controller Memory Buffer (CMB) As Cache
App. No. 18/818,259
→
DATA STORAGE SYSTEMS AND PROCESSES FOR DATA SEARCHING AND ORGANIZATION
App. No. 18/816,377
→
Pipeline Optimization In Low Power Mode Using PMR
App. No. 18/817,040
→
Data Storage Device and Method for Resource Optimization in Video Processing
App. No. 18/813,426
→
OPTIMIZING DATA RETRIEVAL FROM STORAGE DEVICES
App. No. 18/813,213
→
Dynamic Clustering-Based Allocation of Free Chunks at L2P in Thin Provisioning
App. No. 18/811,536
→
HIGH BANDWIDTH FLASH MEMORY CONTAINING A STACK OF BONDED LOGIC AND MEMORY DIE ASSEMBLIES AND METHODS FOR FORMING THE SAME
App. No. 18/811,118
→
Data Storage Device and Method for Video Frame Link-Based Management and Processing
App. No. 18/810,720
→
MULTI SENSE TIME VALLEY SEARCH IN NAND
App. No. 18/808,409
→
NON-CONTACT SEMICONDUCTOR DIE SINGULATION PROCESS
App. No. 18/806,220
→
Data Storage Device and Method for Providing Prolonged High Performance for Tenants in a Multi-Tenancy Environment
App. No. 18/804,492
→
DEVICES AND METHODS FOR TERMINATING TRANSMISSION LINES
App. No. 18/805,352
→
SEMICONDUCTOR PACKAGE HAVING BIFACIAL SEMICONDUCTOR WAFERS
App. No. 18/803,091
→
Data Storage Device and Method for Combining Prediction Models for Read Threshold Calibration
App. No. 18/800,681
→
CROSS-POINT SPIN-ORBIT TORQUE MAGNETORESISTIVE MEMORY ARRAY AND METHOD OF MAKING THE SAME
App. No. 18/798,180
→
PRE-CHARGE AT READ RECOVERY CLOCK FROM BIT LINE SIDE FOR SUB-BLOCK ONE PERFORMANCE IMPROVEMENT
App. No. 18/797,072
→
POWER REALLOCATION FOR MEMORY DEVICE
App. No. 18/775,668
→