STATE SKIP CODING FOR FRACTIONAL BIT-PER-CELL TECH NOLOGY TO IMPROVE DATA RETENTION
A memory apparatus includes memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to convert user data into joint data states comprising one of the plurality of data states for each of the memory cells of pairs of the memory cells and representing a quantity of bits according to a dual-cell encoding scheme. At least some of the plurality of data states of each of the memory cells of the pairs are not used in the dual-cell encoding scheme with ones of the plurality of data states not used for one of the memory cells of the pairs being different than ones of the plurality of data states not used for another of the memory cells of the pairs. The control means also stores the user data using the memory cells of the pairs.
1 . A memory apparatus, comprising:
memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states; and
a control means configured to:
convert user data into joint data states comprising one of the plurality of data states for each of the memory cells of pairs of the memory cells and representing a quantity of bits according to a dual-cell encoding scheme, at least some of the plurality of data states of each of the memory cells of the pairs not used in the dual-cell encoding scheme with ones of the plurality of data states not used for one of the memory cells of the pairs being different than ones of the plurality of data states not used for another of the memory cells of the pairs, and
store the user data using the memory cells of the pairs.
2 . The memory apparatus as set forth in claim 1 , wherein the control means is further configured to skip one of the plurality of data states of one of the memory cells of the pairs in the dual-cell encoding scheme.
3 . The memory apparatus as set forth in claim 2 , wherein the control means is further configured, during a programming operation of the memory cells of the pairs, to lock out the one of the memory cells of the pairs while verifying the one of the plurality of data states skipped.
4 . The memory apparatus as set forth in claim 2 , wherein the plurality of data states includes a highest data state in which the threshold voltage of the memory cells associated therewith is higher than for others of the plurality of data states and a second highest data state in which the threshold voltage of the memory cells associated therewith is higher than for others of the plurality of data states except the highest data state and the control means is further configured to skip the second highest data state for one of the memory cells of the pairs in the dual-cell encoding scheme.
5 . The memory apparatus as set forth in claim 4 , wherein the memory cells of each of the pairs includes a first memory cell and a second memory cell, the quantity of bits is seven bits, the plurality of data states include, in order of the threshold voltage increasing, an erase state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, a seventh data state, an eighth data state, a ninth data state, a tenth data state, and an eleventh data state, the highest data state is the eleventh data state and the second highest data state is the tenth data state, the ones of the plurality of data states partially used for the first memory cell in the dual-cell encoding scheme are the tenth data state and eleventh data state, the ones of the plurality of data states partially used for the second memory cell in the dual-cell encoding scheme are the eighth data state and the ninth data state, the tenth data state is skipped in the dual-cell encoding scheme for the second memory cell.
6 . The memory apparatus as set forth in claim 5 , wherein the user data is stored in the memory cells of the pairs in an upper page and a middle page and a lower page and a half page and the half page includes a remainder of the at least some of the plurality of data states of each of the memory cells of the pairs not used in the dual-cell encoding scheme.
7 . The memory apparatus as set forth in claim 1 , wherein the memory cells of each of the pairs includes a first memory cell and a second memory cell and the first memory cell and the second memory cell of each of each the pairs are disposed physically remote from one another.
8 . A controller in communication with a memory apparatus including memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the controller configured to:
instruct the memory apparatus to convert user data into joint data states comprising one of the plurality of data states for each of the memory cells of pairs of the memory cells and representing a quantity of bits according to a dual-cell encoding scheme, at least some of the plurality of data states of each of the memory cells of the pairs not used in the dual-cell encoding scheme with ones of the plurality of data states not used for one of the memory cells of the pairs being different than ones of the plurality of data states not used for another of the memory cells of the pairs; and
instruct the memory apparatus to store the user data using the memory cells of the pairs.
9 . The controller as set forth in claim 8 , wherein the controller is further configured to instruct the memory apparatus to skip one of the plurality of data states of one of the memory cells of the pairs in the dual-cell encoding scheme.
10 . The controller as set forth in claim 9 , wherein the controller is further configured, during a programming operation of the memory cells of the pairs, instruct the memory apparatus to lock out the one of the memory cells of the pairs while verifying the one of the plurality of data states skipped.
11 . The controller as set forth in claim 9 , wherein the plurality of data states includes a highest data state in which the threshold voltage of the memory cells associated therewith is higher than for others of the plurality of data states and a second highest data state in which the threshold voltage of the memory cells associated therewith is higher than for others of the plurality of data states except the highest data state and the controller is further configured to skip the second highest data state for one of the memory cells of the pairs in the dual-cell encoding scheme.
12 . The controller as set forth in claim 11 , wherein the memory cells of each of the pairs includes a first memory cell and a second memory cell, the quantity of bits is seven bits, the plurality of data states include, in order of the threshold voltage increasing, an erase state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, a seventh data state, an eighth data state, a ninth data state, a tenth data state, and an eleventh data state, the highest data state is the eleventh data state and the second highest data state is the tenth data state, the ones of the plurality of data states partially used for the first memory cell in the dual-cell encoding scheme are the tenth data state and eleventh data state, the ones of the plurality of data states partially used for the second memory cell in the dual-cell encoding scheme are the eighth data state and the ninth data state, the tenth data state is skipped in the dual-cell encoding scheme for the second memory cell.
13 . The controller as set forth in claim 12 , wherein the user data is stored in the memory cells of the pairs in an upper page and a middle page and a lower page and a half page and the half page includes a remainder of the at least some of the plurality of data states of each of the memory cells of the pairs not used in the dual-cell encoding scheme.
14 . A method of operating a memory apparatus including memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the method comprising the steps of:
converting user data into joint data states comprising one of the plurality of data states for each of the memory cells of pairs of the memory cells and representing a quantity of bits according to a dual-cell encoding scheme, at least some of the plurality of data states of each of the memory cells of the pairs not used in the dual-cell encoding scheme with ones of the plurality of data states not used for one of the memory cells of the pairs being different than ones of the plurality of data states not used for another of the memory cells of the pairs; and
storing the user data using the memory cells of the pairs.
15 . The method as set forth in claim 14 , further including the step of skipping one of the plurality of data states of one of the memory cells of the pairs in the dual-cell encoding scheme.
16 . The method as set forth in claim 15 , further including the step of during a programming operation of the memory cells of the pairs, locking out the one of the memory cells of the pairs while verifying the one of the plurality of data states skipped.
17 . The method as set forth in claim 15 , wherein the plurality of data states includes a highest data state in which the threshold voltage of the memory cells associated therewith is higher than for others of the plurality of data states and a second highest data state in which the threshold voltage of the memory cells associated therewith is higher than for others of the plurality of data states except the highest data state and the method further includes the step of skipping the second highest data state for one of the memory cells of the pairs in the dual-cell encoding scheme.
18 . The method as set forth in claim 17 , wherein the memory cells of each of the pairs includes a first memory cell and a second memory cell, the quantity of bits is seven bits, the plurality of data states include, in order of the threshold voltage increasing, an erase state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, a seventh data state, an eighth data state, a ninth data state, a tenth data state, and an eleventh data state, the highest data state is the eleventh data state and the second highest data state is the tenth data state, the ones of the plurality of data states partially used for the first memory cell in the dual-cell encoding scheme are the tenth data state and eleventh data state, the ones of the plurality of data states partially used for the second memory cell in the dual-cell encoding scheme are the eighth data state and the ninth data state, the tenth data state is skipped in the dual-cell encoding scheme for the second memory cell.
19 . The method as set forth in claim 18 , wherein the user data is stored in the memory cells of the pairs in an upper page and a middle page and a lower page and a half page and the half page includes a remainder of the at least some of the plurality of data states of each of the memory cells of the pairs not used in the dual-cell encoding scheme.
20 . The method as set forth in claim 14 , wherein the memory cells of each of the pairs includes a first memory cell and a second memory cell and the first memory cell and the second memory cell of each of each the pairs are disposed physically remote from one another.