THREE-DIMENSIONAL MEMORY DEVICE CONTAINING THERMALLY CONDUCTIVE AND INSULATING TRENCH FILL STRUCTURE AND METHODS FOR FORMING THE SAME USING LASER ANNEALING

1 . A memory device, comprising:

alternating stacks that are laterally spaced apart from each other by lateral isolation trench fill structures, wherein each of the alternating stacks comprises a respective vertically alternating sequence of insulating layers and electrically conductive layers;

memory openings vertically extending through a respective one of the alternating stacks;

memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements; and

a polycrystalline semiconductor source layer underlying the alternating stack and contacting bottom surfaces of the vertical semiconductor channels,

wherein each of the lateral isolation trench fill structures comprises a thermally conductive trench fill material portion that is vertically spaced from the polycrystalline semiconductor source layer by a thermally insulating material.

2 . The memory device of claim 1 , wherein:

the polycrystalline semiconductor source layer has topmost surface within a first horizontal plane;

each of the lateral isolation trench fill structures further comprises a thermally insulating spacer; and

the thermally conductive trench fill material portion is embedded within the thermally insulating spacer and having a bottommost surface that is vertically spaced from the first horizontal plane by a vertical spacing that is greater than a maximum lateral thickness of the thermally insulating spacer.

3 . The memory device of claim 2 , wherein within each of the lateral isolation trench fill structures, the thermally insulating spacer has a variable lateral thickness that increases with a vertical distance from the first horizontal plane and all sidewall surfaces of the thermally conductive trench fill material portion are in direct contact with the thermally insulating spacer.

4 . The memory device of claim 2 , wherein:

the thermally insulating spacer comprises a bottom portion located below the thermally conductive trench fill material portion; and

the thermally conductive trench fill material portion is vertically spaced from the polycrystalline semiconductor source layer by the thermally insulating material of the bottom portion of the thermally insulating spacer.

5 . The memory device of claim 4 , wherein the bottom portion of the thermally insulating spacer contacts both the polycrystalline semiconductor source layer and the bottom portion of the thermally conductive trench fill material portion that is proximal to the first horizontal plane.

6 . The memory device of claim 2 , further comprising backside thermal isolation structures located between neighboring pairs of the alternating stacks and interposed between a respective one of the lateral isolation trench fill structures and the first horizontal plane.

7 . The memory device of claim 6 , wherein:

the thermally conductive trench fill material portion is vertically spaced from the polycrystalline semiconductor source layer by the thermally insulating material of a respective one of the backside thermal isolation structures; and

each of the backside thermal isolation structures contacts the polycrystalline semiconductor source layer, a respective one of the thermally insulating spacers, and a respective one of the thermally conductive trench fill material portions.

8 . The memory device of claim 2 , further comprising contact-level dielectric layers overlying a respective one of the alternating stacks and laterally spaced apart from each other by the lateral isolation trench fill structures.

9 . The memory device of claim 8 , wherein top surfaces of the lateral isolation trench fill structures are located entirely within a second horizontal plane including top surfaces of the contact-level dielectric layers.

10 . The memory device of claim 2 , wherein bottom surfaces of the thermally conductive trench fill material portions are more proximal to the first horizontal plane than any of the electrically conductive layers in the alternating stacks are to the first horizontal plane.

11 . The memory device of claim 2 , wherein bottom surfaces of the lateral isolation trench fill structures are located below the first horizontal plane.

12 . The memory device of claim 2 , wherein bottom portions of the thermally insulating spacers that underlie a respective one of the thermally conductive trench fill material portions have a respective vertical extent that is greater than the vertical spacing.

13 . The memory device of claim 1 , wherein the thermally insulating material has a thermal conductivity of less than 20 W/m*K, and the thermally conductive trench fill material portions comprise a refractory metal or a refractory metal nitride.

14 . The memory device of claim 13 , wherein:

the thermally insulating material comprises silicon oxide;

the thermally conductive trench fill material portions comprise tungsten; and

the polycrystalline semiconductor source layer comprises doped polysilicon.

15 . A method of forming a memory device, comprising:

forming alternating stacks laterally spaced from each other by lateral isolation trenches over a carrier substrate, wherein each of the alternating stacks comprises a respective vertically alternating sequence of insulating layers and electrically conductive layers and embeds a respective set of memory opening fill structures, and wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel and a respective stack of memory elements located at levels of the electrically conductive layers;

forming lateral isolation trench fill structures in the lateral isolation trenches by anisotropically depositing a thermally insulating material in peripheral regions of the lateral isolation trenches and by subsequently depositing a thermally conductive trench fill material in center regions of the lateral isolation trenches, wherein each of the lateral isolation trench fill structures comprises a thermally insulating spacer and a thermally conductive trench fill material portion embedded within the thermally insulating spacer;

removing the carrier substrate and exposing bottom end portions of the vertical semiconductor channels;

depositing an amorphous semiconductor source layer on the exposed bottom end portions of the vertical semiconductor channels; and

crystallizing the amorphous semiconductor source layer into a polycrystalline semiconductor source layer by laser annealing.

16 . The method of claim 15 , wherein the thermally conductive trench fill material portion has a bottommost surface that is vertically spaced from a bottom surface of the thermally insulating spacer by a vertical distance that is greater than a maximum lateral thickness of the thermally insulating spacer at a top surface of the lateral isolation trench fill structures.

17 . The method of claim 15 , wherein:

the method further comprises forming a sacrificial etch-stop layer over the carrier substrate;

the alternating stacks are formed over the sacrificial etch-stop layer;

the lateral isolation trenches extend into an upper portion of the sacrificial etch-stop layer; and

the method further comprises removing the sacrificial etch-stop layer after removing the carrier substrate selectively to the lateral isolation trench fill structures.

18 . A method of forming a memory device, comprising:

forming alternating stacks laterally spaced from each other by lateral isolation trenches over a carrier substrate, wherein each of the alternating stacks comprises a respective vertically alternating sequence of insulating layers and electrically conductive layers and embeds a respective set of memory opening fill structures, and wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel and a respective stack of memory elements located at levels of the electrically conductive layers;

forming lateral isolation trench fill structures in the lateral isolation trenches by sequentially depositing a thermally and electrically insulating material and a thermally conductive trench fill material, wherein each of the lateral isolation trench fill structures comprises a thermally insulating spacer and a thermally conductive trench fill material portion embedded within the thermally insulating spacer;

removing the carrier substrate;

forming backside shallow trenches by removing bottom portions of the thermally insulating spacers;

forming backside thermal isolation structures in the backside shallow trenches;

exposing bottom end portions of the vertical semiconductor channels;

depositing an amorphous semiconductor source layer on the exposed bottom end portions of the vertical semiconductor channels; and

crystallizing the amorphous semiconductor source layer into a polycrystalline semiconductor source layer by laser annealing.

19 . The method of claim 18 , wherein:

the backside thermal isolation structures comprise silicon oxide;

the thermally conductive trench fill material portions comprise tungsten; and

the polycrystalline semiconductor source layer comprises doped polysilicon.

20 . The method of claim 18 , further comprising:

forming a sacrificial etch-stop layer and a source isolation dielectric layer over the carrier substrate, wherein the alternating stacks are formed over the source isolation dielectric layer;

removing the sacrificial etch-stop layer after removing the carrier substrate selectively to the lateral isolation trench fill structures;

forming a patterned photoresist layer on the source isolation dielectric layer such that areas of openings in the patterned photoresist layer overlie areas of the thermally conductive trench fill material portions; and

performing an anisotropic etch process employing the patterned photoresist layer as an etch mask to form the backside shallow trenches.