IN-PLACE ERASE TECHNIQUES FOR NONVOLATILE MEMORY DEVICES
The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells of a selected word line of the plurality of word lines are programmed to contain data. The memory device also includes circuitry that is configured to perform a read operation on the memory cells of the selected word line using a reference voltage. In response to the read operation passing, the circuitry is configured to end the read operation. In response to the read operation failing, the circuitry is configured to perform an in-place erase operation on only the selected word line to lower threshold voltages of a plurality of selected memory cells of the selected word line while a plurality of unselected memory cells of the selected word line do not have their threshold voltages lowered.
1 . A method of operating a memory package, comprising the steps of:
preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the memory cells of a selected word line of the plurality of word lines being programmed to contain data;
performing a read operation on the memory cells of the selected word line using a reference voltage;
in response to the read operation passing, ending the read operation; and
in response to the read operation failing, performing an in-place erase operation on only the selected word line to lower threshold voltages of a plurality of selected memory cells of the selected word line while a plurality of unselected memory cells of the selected word line do not have their threshold voltages lowered.
2 . The method as set forth in claim 1 , wherein the memory cells of the selected word line are programmed according to a single bit per memory cell storage scheme that includes a first data state that is associated with a first threshold range and a second data state that is associated with a second threshold voltage range that is greater than the first threshold voltage range.
3 . The method as set forth in claim 2 , wherein the plurality of selected memory cells are in the first data state.
4 . The method as set forth in claim 2 , wherein the read operation is a first read operation and the reference voltage is a second reference voltage; and
wherein prior to the step of performing the in-place erase operation, the method includes the step of performing a second read operation on the memory cells of the selected word line at a first reference voltage that is greater than the second reference voltage.
5 . The method as set forth in claim 4 , wherein in response to the second read operation passing, the method continues with the steps of:
performing a third read operation on the memory cells of the selected word line at a third reference voltage that is less than the second reference voltage, and
setting the memory cells of the selected word line that are determined to have threshold voltages between the first and third reference voltages as the selected memory cells for the in-place erase operation.
6 . The method as set forth in claim 4 , wherein in response to the second read operation failing, the method continues with the steps of:
identifying with an error correction code engine a plurality of memory cells that failed the second read operation, and
setting the plurality of memory cells that failed the second read operation as the selected memory cells for the in-place erase operation.
7 . The method as set forth in claim 1 , wherein during the in-place erase operation, a higher voltage is applied to a plurality of bit lines that are coupled to the selected memory cells and a lower voltage is applied to a plurality of bit lines that are coupled to the unselected memory cells.
8 . A memory device, comprising:
a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the memory cells of a selected word line of the plurality of word lines being programmed to contain data;
circuitry that is configured to;
perform a read operation on the memory cells of the selected word line using a reference voltage;
in response to the read operation passing, end the read operation; and
in response to the read operation failing, perform an in-place erase operation on only the selected word line to lower threshold voltages of a plurality of selected memory cells of the selected word line while a plurality of unselected memory cells of the selected word line do not have their threshold voltages lowered.
9 . The memory device as set forth in claim 8 , wherein the memory cells of the selected word line are programmed according to a single bit per memory cell storage scheme that includes a first data state that is associated with a first threshold range and a second data state that is associated with a second threshold voltage range that is greater than the first threshold voltage range.
10 . The memory device as set forth in claim 9 , wherein the plurality of selected memory cells are in the first data state.
11 . The memory device as set forth in claim 9 , wherein the read operation is a first read operation and the reference voltage is a second reference voltage; and
wherein prior to the step of performing the in-place erase operation, the circuitry performs a second read operation on the memory cells of the selected word line at a first reference voltage that is greater than the second reference voltage.
12 . The memory device as set forth in claim 11 , wherein in response to the second read operation passing, the circuitry is configured to:
perform a third read operation on the memory cells of the selected word line at a third reference voltage that is less than the second reference voltage, and
set the memory cells of the selected word line that are determined to have threshold voltages between the first and third reference voltages as the selected memory cells for the in-place erase operation.
13 . The memory device as set forth in claim 11 , wherein in response to the second read operation failing, the circuitry is configured to:
identify with an error correction code engine a plurality of memory cells that failed the second read operation, and
set the plurality of memory cells that failed the second read operation as the selected memory cells for the in-place erase operation.
14 . The memory device as set forth in claim 8 , wherein during the in-place erase operation, the circuitry applies a higher voltage to a plurality of bit lines that are coupled to the selected memory cells and a lower voltage to a plurality of bit lines that are coupled to the unselected memory cells.
15 . A computing system, comprising:
a processing unit;
a plurality of non-volatile memory packages that are in electrical communication with the processing unit; and
at least one of the non-volatile memory packages including a memory block that has an array of memory cells that are arranged in a plurality of word lines, the memory cells of a selected word line of the plurality of word lines being programmed to contain data and including circuitry that is configured to;
perform a read operation on the memory cells of the selected word line using a reference voltage;
in response to the read operation passing, end the read operation; and
in response to the read operation failing, perform an in-place erase operation on only the selected word line to lower threshold voltages of a plurality of selected memory cells of the selected word line while a plurality of unselected memory cells of the selected word line do not have their threshold voltages lowered.
16 . The computing system as set forth in claim 15 , wherein the memory cells of the selected word line are programmed according to a single bit per memory cell storage scheme that includes a first data state that is associated with a first threshold range and a second data state that is associated with a second threshold voltage range that is greater than the first threshold voltage range.
17 . The computing system as set forth in claim 16 , wherein the plurality of selected memory cells are in the first data state.
18 . The computing system as set forth in claim 16 , wherein the read operation is a first read operation and the reference voltage is a second reference voltage; and
wherein prior to the step of performing the in-place erase operation, the circuitry performs a second read operation on the memory cells of the selected word line at a first reference voltage that is greater than the second reference voltage.
19 . The computing system as set forth in claim 18 , wherein in response to the second read operation passing, the circuitry is configured to:
perform a third read operation on the memory cells of the selected word line at a third reference voltage that is less than the second reference voltage, and
set the memory cells of the selected word line that are determined to have threshold voltages between the first and third reference voltages as the selected memory cells for the in-place erase operation.
20 . The computing system as set forth in claim 18 , wherein in response to the second read operation failing, the circuitry is configured to:
identify with an error correction code engine a plurality of memory cells that failed the second read operation, and
set the plurality of memory cells that failed the second read operation as the selected memory cells for the in-place erase operation.